ATSAMA5D21

MCU_Microchip_SAMA

ARM Cortex-A5 MPU, 500 MHz max, 1x SDIO/SD-CARD/eMMC/QSPI memory, 128 kB SRAM, 16-bit bus DDR2/DDR3 RAM, 1.1-1.32 V, 72 GPIO, TFBGA-196

Symbol

196 pins

Units: 10
Kind: part
Grid: on 1.27 mm

Footprint

196 pads

Library: Package_BGA
Mount: smd
Courtyard: 13 × 13 mm
Link: exact

3D model

none

no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

Every pin on the symbol has a pad on the footprint.

Pin	Name	Type	Pad
A1	PB10	bidirectional	A1
A2	PB8	bidirectional	A2
A3	PB6	bidirectional	A3
A4	PB4	bidirectional	A4
A5	PB1	bidirectional	A5
A6	PB0	bidirectional	A6
A7	DDR_D1	bidirectional	A7
A8	DDR_DQSN0	output	A8
A9	DDR_D4	bidirectional	A9
B1	PB11	bidirectional	B1
B2	PB12	bidirectional	B2
B3	PB9	bidirectional	B3
B4	PB7	bidirectional	B4
B5	PB3	bidirectional	B5
B6	PB2	bidirectional	B6
B7	DDR_D0	bidirectional	B7
B8	DDR_DQS0	output	B8
B9	DDR_D3	bidirectional	B9
C1	PB13	bidirectional	C1
C2	PB17	bidirectional	C2
C3	PB20	bidirectional	C3
C4	PB19	bidirectional	C4
C5	PB16	bidirectional	C5
C6	VDDIODDR	power_in	C6
C7	GNDIODDR	power_in	C7
C8	DDR_D2	bidirectional	C8
C9	DDR_D5	bidirectional	C9
D1	PB21	bidirectional	D1
D2	PB22	bidirectional	D2
D3	PB24	bidirectional	D3
D4	PB18	bidirectional	D4
D5	PB14	bidirectional	D5
D6	PB5	bidirectional	D6
D7	VDDIOP0	power_in	D7
D8	DDR_DQM0	output	D8
D9	DDR_A7	output	D9
E1	PB23	bidirectional	E1
E2	PB26	bidirectional	E2
E3	PB25	bidirectional	E3
E4	GNDIOP0	power_in	E4
E5	PB15	bidirectional	E5
E6	PB27	bidirectional	E6
E7	GNDIOP0	passive	E7
E8	VDDCORE	power_in	E8
E9	GNDIODDR	passive	E9
F1	PB28	bidirectional	F1
F2	PB30	bidirectional	F2
F3	PD8	bidirectional	F3
F4	VDDIOP0	passive	F4
F5	PD7	bidirectional	F5
F6	PB29	bidirectional	F6
F7	PB31	bidirectional	F7
F8	GNDCORE	power_in	F8
F9	DDR_A10	output	F9
G1	PD16	bidirectional	G1
G2	PD17	bidirectional	G2
G3	PD18	bidirectional	G3
G4	PD10	bidirectional	G4
G5	PD9	bidirectional	G5
G6	PD14	bidirectional	G6
G7	GNDCORE	passive	G7
G8	VDDCORE	passive	G8
G9	GNDCORE	passive	G9
H1	PD11	bidirectional	H1
H2	VDDANA	passive	H2
H3	PD13	bidirectional	H3
H4	PD19	bidirectional	H4
H5	PD15	bidirectional	H5
H6	PD12	bidirectional	H6
H7	GNDCORE	passive	H7
H8	VDDCORE	passive	H8
H9	VDDCORE	passive	H9
J1	PD20	bidirectional	J1
J2	GNDANA	passive	J2
J3	PD22	bidirectional	J3
J4	GNDCORE	passive	J4
J5	VDDCORE	passive	J5
J6	GNDAUDIOPLL	power_in	J6
J7	CLK_AUDIO	output	J7
J8	PC5	bidirectional	J8
J9	PC8	bidirectional	J9
K1	PD21	bidirectional	K1
K2	PD23	bidirectional	K2
K3	VDDANA	power_in	K3
K4	GNDANA	power_in	K4
K5	PIOBU0	bidirectional	K5
K6	VDDAUDIOPLL	power_in	K6
K7	VDDUTMII	power_in	K7
K8	VDDIOP1	power_in	K8
K9	GNDIOP1	power_in	K9
L1	XOUT32	output	L1
L2	ADVREF	power_in	L2
L3	PIOBU1	bidirectional	L3
L4	JTAGSEL	input	L4
L5	PIOBU4	bidirectional	L5
L6	GNDDPLL	power_in	L6
L7	VBG	power_in	L7
L8	GNDUTMII	power_in	L8
L9	PA18	bidirectional	L9
M1	XIN32	input	M1
M2	TST	input	M2
M3	PIOBU2	bidirectional	M3
M4	VDDBU	power_in	M4
M5	GNDBU	power_in	M5
M6	PIOBU5	bidirectional	M6
M7	VDDUTMIC	power_in	M7
M8	GNDUTMIC	power_in	M8
M9	PA20	bidirectional	M9
N1	SHDN	output	N1
N2	COMPP	input	N2
N3	~{RST}	input	N3
N4	PIOBU3	bidirectional	N4
N5	VDDOSC	power_in	N5
N6	GNDOSC	power_in	N6
N7	HHSDPA	bidirectional	N7
N8	HHSDPB	bidirectional	N8
N9	PA19	bidirectional	N9
P1	WKUP	input	P1
P2	COMPN	input	P2
P3	VDDPLLA	power_in	P3
P4	GNDPLLA	power_in	P4
P5	XIN	input	P5
P6	XOUT	output	P6
P7	HHSDMA	bidirectional	P7
P8	HHSDMB	bidirectional	P8
P9	PA22	bidirectional	P9
A10	DDR_D6	bidirectional	A10
A11	DDR_A11	output	A11
A12	DDR_A3	output	A12
A13	DDR_CLK	output	A13
A14	DDR_WE	output	A14
B10	DDR_D7	bidirectional	B10
B11	DDR_A12	output	B11
B12	DDR_A2	output	B12
B13	DDR_CLKN	output	B13
B14	DDR_A6	output	B14
C10	DDR_A8	output	C10
C11	DDR_A1	output	C11
C12	DDR_VREF	power_in	C12
C13	DDR_CAS	output	C13
C14	DDR_RAS	output	C14
D10	DDR_A9	output	D10
D11	DDR_A4	output	D11
D12	GNDIODDR	passive	D12
D13	~{DDR_RESET}	output	D13
D14	DDR_A5	output	D14
E10	VDDIODDR	passive	E10
E11	DDR_A0	output	E11
E12	VDDIODDR	passive	E12
E13	DDR_A13	output	E13
E14	DDR_CKE	output	E14
F10	DDR_CAL	input	F10
F11	DDR_CS	output	F11
F12	GNDIODDR	passive	F12
F13	DDR_BA0	output	F13
F14	DDR_BA2	output	F14
G10	VDDIODDR	passive	G10
G11	GNDIODDR	passive	G11
G12	VDDIODDR	passive	G12
G13	DDR_BA1	output	G13
G14	DDR_DQM1	output	G14
H10	GNDIODDR	passive	H10
H11	VDDIODDR	passive	H11
H12	DDR_VREF	passive	H12
H13	DDR_D8	bidirectional	H13
H14	DDR_D9	bidirectional	H14
J10	VDDIODDR	passive	J10
J11	GNDIODDR	passive	J11
J12	DDR_D14	bidirectional	J12
J13	DDR_D10	bidirectional	J13
J14	DDR_D11	bidirectional	J14
K10	PC3	bidirectional	K10
K11	VDDFUSE	power_in	K11
K12	DDR_D15	bidirectional	K12
K13	DDR_DQSN1	output	K13
K14	DDR_DQS1	output	K14
L10	PA25	bidirectional	L10
L11	VDDIOP1	passive	L11
L12	GNDIOP1	passive	L12
L13	DDR_D12	bidirectional	L13
L14	DDR_D13	bidirectional	L14
M10	PA21	bidirectional	M10
M11	PA28	bidirectional	M11
M12	PA31	bidirectional	M12
M13	PC0	bidirectional	M13
M14	PC7	bidirectional	M14
N10	PA24	bidirectional	N10
N11	PA29	bidirectional	N11
N12	PA30	bidirectional	N12
N13	PC2	bidirectional	N13
N14	PC6	bidirectional	N14
P10	PA23	bidirectional	P10
P11	PA26	bidirectional	P11
P12	PA27	bidirectional	P12
P13	PC1	bidirectional	P13
P14	PC4	bidirectional	P14

Provenance

Source: kicad-symbols
Credit: KiCad Libraries Contributors
Licence: CC-BY-SA-4.0-with-KiCad-exception
Link method: exact
Cross-check: passed