STM32MP151CADx

MCU_ST_STM32MP1

STMicroelectronics Arm Cortex-A7 MCU, 0KB flash, 708KB RAM, 98 GPIO, TFBGA257

Symbol

257 pins
Schematic symbol for STM32MP151CADx
Units
1
Kind
part
Grid
on 1.27 mm

Footprint

257 pads
Footprint for STM32MP151CADx
Library
Package_BGA
Mount
smd
Courtyard
12 × 12 mm
Link
exact

3D model

none
no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

Every pin on the symbol has a pad on the footprint.

PinNameTypePad
A1VSSpower_inA1
A2PD1bidirectionalA2
A3PB7bidirectionalA3
A4PC6bidirectionalA4
A6VSSpassiveA6
A7PD3bidirectionalA7
A9PC8bidirectionalA9
B1PG15bidirectionalB1
B2PE6bidirectionalB2
B3PD7bidirectionalB3
B4PA15bidirectionalB4
B5PG6bidirectionalB5
B6PB4bidirectionalB6
B7PE5bidirectionalB7
B8PA8bidirectionalB8
B9PC9bidirectionalB9
C1PE12bidirectionalC1
C2PE0bidirectionalC2
C3PD4bidirectionalC3
C4PD5bidirectionalC4
C5PD0bidirectionalC5
C6PA9bidirectionalC6
C7PB3bidirectionalC7
C8PB15bidirectionalC8
C9PB9bidirectionalC9
D1PG12bidirectionalD1
D2PE11bidirectionalD2
D3PE15bidirectionalD3
E1PD8bidirectionalE1
E2NRSTinputE2
E3PE13bidirectionalE3
F2PC15bidirectionalF2
F3VSSpassiveF3
G1VSSpassiveG1
G2PC14bidirectionalG2
G3PC13bidirectionalG3
H1BOOT2inputH1
H2PH0bidirectionalH2
H3BOOT0inputH3
J2PH1bidirectionalJ2
J3NRST_COREinputJ3
K1PWR_LPoutputK1
K2PDR_ON_COREbidirectionalK2
K3BOOT1inputK3
L1PA14bidirectionalL1
L2PA13bidirectionalL2
L3PDR_ONbidirectionalL3
M2PWR_ONoutputM2
M3VREF+inputM3
N1VSSpassiveN1
N2PA3bidirectionalN2
N3PA0bidirectionalN3
P1PE2bidirectionalP1
P2PC2bidirectionalP2
P3PC3bidirectionalP3
R2PG14bidirectionalR2
R3PG13bidirectionalR3
T1PA1bidirectionalT1
T2PC1bidirectionalT2
T3PA2bidirectionalT3
U1PB1bidirectionalU1
U2PB0bidirectionalU2
U3PB11bidirectionalU3
U4PC0bidirectionalU4
U5PB10bidirectionalU5
U6PG11bidirectionalU6
U7PG10bidirectionalU7
U8PD11bidirectionalU8
U9VSSpassiveU9
V1PC5bidirectionalV1
V2PC4bidirectionalV2
V3PB12bidirectionalV3
V4PB8bidirectionalV4
V5PB5bidirectionalV5
V6PG8bidirectionalV6
V7PE7bidirectionalV7
V8PF8bidirectionalV8
V9PF9bidirectionalV9
W1VSSpassiveW1
W2PA7bidirectionalW2
W3PA6bidirectionalW3
W4PF11bidirectionalW4
W5VSSpassiveW5
W7PF7bidirectionalW7
W8PG9bidirectionalW8
1A1PE1bidirectional1A1
1A2PD10bidirectional1A2
1A3PE3bidirectional1A3
1A4PB14bidirectional1A4
1A5PD2bidirectional1A5
1A6VSSpassive1A6
1A7VDD1V2_Unusedpower_in1A7
1A8DDR_ZQbidirectional1A8
1A9DDR_A7bidirectional1A9
1B1PD6bidirectional1B1
1B2PE14bidirectional1B2
1B3VDDCOREpower_in1B3
1B4PC12bidirectional1B4
1B5VDDCOREpower_in1B5
1B6VDDA1V8_Unusedpower_in1B6
1B7VDD1V2_Unusedpower_in1B7
1B8VSSpassive1B8
1B9VDDQ_DDRpower_in1B9
1C1PD9bidirectional1C1
1C2PD15bidirectional1C2
1C3VSSpassive1C3
1C4VDDCOREpower_in1C4
1C5VSSpassive1C5
1C6VDDCOREpower_in1C6
1C7VSSpassive1C7
1C8DDR_DTO1bidirectional1C8
1C9DDR_A5bidirectional1C9
1D1VBATpower_in1D1
1D2VSSpassive1D2
1D3VDDCOREpower_in1D3
1D4VSSpassive1D4
1D5VDDCOREpower_in1D5
1D6VSSpassive1D6
1D7VDDCOREpower_in1D7
1D8DDR_DTO0bidirectional1D8
1D9VDDQ_DDRpower_in1D9
1E1PD14bidirectional1E1
1E2VDDpower_in1E2
1E3VSSpassive1E3
1E4VDDCOREpower_in1E4
1E5VSSpassive1E5
1E6VDDCOREpower_in1E6
1E7VSSpassive1E7
1E8VDDCOREpower_in1E8
1E9DDR_RASNbidirectional1E9
1F1VDDApower_in1F1
1F2VDDApower_in1F2
1F3VDDpower_in1F3
1F4VSSpassive1F4
1F5VDDCOREpower_in1F5
1F6VSSpassive1F6
1F7VDDCOREpower_in1F7
1F8DDR_ATObidirectional1F8
1F9VDDQ_DDRpower_in1F9
1G1VSSApower_in1G1
1G2VSSpassive1G2
1G3VDDpower_in1G3
1G4VDDpower_in1G4
1G5VSSpassive1G5
1G6VDDCOREpower_in1G6
1G7VSSpassive1G7
1G8VDDCOREpower_in1G8
1G9DDR_A6bidirectional1G9
1H1PA5bidirectional1H1
1H2VSSpassive1H2
1H3VSSpassive1H3
1H4VSSpassive1H4
1H5VDDA1V8_REGpower_in1H5
1H6VSSpassive1H6
1H7VDD3V3_USBpower_in1H7
1H8VSSpassive1H8
1H9VDDQ_DDRpower_in1H9
1J1PA4bidirectional1J1
1J2PB13bidirectional1J2
1J3VDDpower_in1J3
1J4PE9bidirectional1J4
1J5VSSpassive1J5
1J6VDDA1V1_REGpower_in1J6
1J7PF10bidirectional1J7
1J8USB_RREFbidirectional1J8
1J9VSSpassive1J9
A10PE4bidirectionalA10
A12DNUno_connectA12
A13DNUno_connectA13
A15JTDObidirectionalA15
A16JTCKbidirectionalA16
A17DDR_DQ0bidirectionalA17
A18DDR_DQ1bidirectionalA18
A19VSSpassiveA19
B10PC10bidirectionalB10
B11DNUno_connectB11
B12DNUno_connectB12
B13DNUno_connectB13
B14NJTRSTbidirectionalB14
B15JTDIbidirectionalB15
B16DDR_DQ3bidirectionalB16
B17DDR_DQ7bidirectionalB17
B18DDR_DQS0NbidirectionalB18
B19DDR_DQS0PbidirectionalB19
C10PC7bidirectionalC10
C11PC11bidirectionalC11
C12DNUno_connectC12
C13VDD_Unusedpower_inC13
C14VSSpassiveC14
C15JTMSbidirectionalC15
C16DDR_RESETNbidirectionalC16
C17DDR_DQM0bidirectionalC17
C18DDR_DQ2bidirectionalC18
C19DDR_DQ6bidirectionalC19
D17VSSpassiveD17
D18DDR_DQ4bidirectionalD18
D19DDR_DQ5bidirectionalD19
E17DDR_A13bidirectionalE17
E18DDR_A9bidirectionalE18
F17DDR_A2bidirectionalF17
F18VSSpassiveF18
F19DDR_A3bidirectionalF19
G17VSSpassiveG17
G18DDR_A0bidirectionalG18
G19DDR_BA0bidirectionalG19
H17DDR_BA2bidirectionalH17
H18DDR_ODTbidirectionalH18
J17DDR_CSNbidirectionalJ17
J18DDR_WENbidirectionalJ18
J19DDR_CASNbidirectionalJ19
K17VSSpassiveK17
K18DDR_CLKNbidirectionalK18
K19VSSpassiveK19
L17DDR_CLKPbidirectionalL17
L18DDR_A15bidirectionalL18
M17DDR_A10bidirectionalM17
M18DDR_A12bidirectionalM18
M19DDR_A1bidirectionalM19
N17VSSpassiveN17
N18DDR_A14bidirectionalN18
N19DDR_A11bidirectionalN19
P17DDR_CKEbidirectionalP17
P18DDR_BA1bidirectionalP18
R17DDR_A4bidirectionalR17
R18DDR_DQ8bidirectionalR18
R19VSSpassiveR19
T17DDR_A8bidirectionalT17
T18DDR_DQ13bidirectionalT18
T19DDR_DQ10bidirectionalT19
U10PF6bidirectionalU10
U11BYPASS_REG1V8bidirectionalU11
U12PE8bidirectionalU12
U13PD13bidirectionalU13
U14PD12bidirectionalU14
U15PA11bidirectionalU15
U16PA10bidirectionalU16
U17DDR_DQ14bidirectionalU17
U18DDR_DQS1NbidirectionalU18
U19DDR_DQ9bidirectionalU19
V10USB_DP2bidirectionalV10
V11PG7bidirectionalV11
V12PE10bidirectionalV12
V13PB2bidirectionalV13
V14USB_DP1bidirectionalV14
V15PA12bidirectionalV15
V16OTG_VBUSbidirectionalV16
V17DDR_DQ15bidirectionalV17
V18DDR_DQM1bidirectionalV18
V19DDR_DQS1PbidirectionalV19
W10USB_DM2bidirectionalW10
W11PB6bidirectionalW11
W13VSSpassiveW13
W14USB_DM1bidirectionalW14
W16DDR_VREFbidirectionalW16
W17DDR_DQ12bidirectionalW17
W18DDR_DQ11bidirectionalW18
W19VSSpassiveW19

Provenance

Credit
KiCad Libraries Contributors
Licence
CC-BY-SA-4.0-with-KiCad-exception
Link method
exact
Cross-check
passed
STM32MP151CADx — MCU_ST_STM32MP1 | Trace Catalog