STM32MP153FABx

MCU_ST_STM32MP1

STMicroelectronics Arm Cortex-A7 MCU, 0KB flash, 708KB RAM, 98 GPIO, LFBGA354

Symbol

354 pins
Schematic symbol for STM32MP153FABx
Units
1
Kind
part
Grid
on 1.27 mm

Footprint

354 pads
Footprint for STM32MP153FABx
Library
Package_BGA
Mount
smd
Courtyard
18 × 18 mm
Link
exact

3D model

none
no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

Every pin on the symbol has a pad on the footprint.

PinNameTypePad
A1VSSpower_inA1
A2PG15bidirectionalA2
A3PD0bidirectionalA3
A4PD1bidirectionalA4
A5PE3bidirectionalA5
A6PG6bidirectionalA6
A7PB3bidirectionalA7
A8PB15bidirectionalA8
A9PC7bidirectionalA9
B1PE1bidirectionalB1
B2VSSpassiveB2
B3PE6bidirectionalB3
B4PD7bidirectionalB4
B5PB7bidirectionalB5
B6VSSpassiveB6
B7PE5bidirectionalB7
B8PA8bidirectionalB8
B9PB4bidirectionalB9
C1PE11bidirectionalC1
C2PE13bidirectionalC2
C3VSSpassiveC3
C4PE0bidirectionalC4
C5PD10bidirectionalC5
C6PD3bidirectionalC6
C7PA15bidirectionalC7
C8PA9bidirectionalC8
C9PB14bidirectionalC9
D1VSSpassiveD1
D2PE12bidirectionalD2
D3PE14bidirectionalD3
D4VSSpassiveD4
D5VSSpassiveD5
D6PD4bidirectionalD6
D7PD5bidirectionalD7
D8VSSpassiveD8
D9PB9bidirectionalD9
E1PE15bidirectionalE1
E2VSSpassiveE2
E3PD6bidirectionalE3
E4VSSpassiveE4
E5VSSpassiveE5
E6VSSpassiveE6
E7VDDCOREpower_inE7
E8VSSpassiveE8
E9VDDCOREpower_inE9
F1PG12bidirectionalF1
F2PD8bidirectionalF2
F3PD14bidirectionalF3
F4VDDCOREpower_inF4
F5VSSpassiveF5
F6VDDCOREpower_inF6
F7VSSpassiveF7
F8VDDCOREpower_inF8
F9VSSpassiveF9
G1PD15bidirectionalG1
G2VSSpassiveG2
G3PD9bidirectionalG3
G4VSSpassiveG4
G5VDDCOREpower_inG5
G6VSSpassiveG6
G7VDDCOREpower_inG7
G8VSSpassiveG8
G9VDDCOREpower_inG9
H1PC14bidirectionalH1
H2PC15bidirectionalH2
H3VBATpower_inH3
H4VDDCOREpower_inH4
H5VSSpassiveH5
H6VDDCOREpower_inH6
H7VSSpassiveH7
H8VDDCOREpower_inH8
H9VSSpassiveH9
J1NRSTinputJ1
J2NRST_COREinputJ2
J3VSSpassiveJ3
J4VSS_PLLpower_inJ4
J5VDD_PLLpower_inJ5
J6VSSpassiveJ6
J7VDDCOREpower_inJ7
J8VSSpassiveJ8
J9VDDCOREpower_inJ9
K1BOOT0inputK1
K2VSSpassiveK2
K3PC13bidirectionalK3
K4BOOT1inputK4
K5VSSpassiveK5
K6VDDpower_inK6
K7VSSpassiveK7
K8VDDCOREpower_inK8
K9VSSpassiveK9
L1PWR_ONoutputL1
L2BOOT2inputL2
L3VDD_ANApower_inL3
L4VSS_ANApower_inL4
L5VDDpower_inL5
L6VSSpassiveL6
L7VDDpower_inL7
L8VSSpassiveL8
L9VDDCOREpower_inL9
M1PH0bidirectionalM1
M2PH1bidirectionalM2
M3VREF-inputM3
M4VDDApower_inM4
M5VSSpassiveM5
M6VDDpower_inM6
M7VSSpassiveM7
M8VDDpower_inM8
M9VSSpassiveM9
N1PDR_ON_COREbidirectionalN1
N2PDR_ONbidirectionalN2
N3VREF+inputN3
N4VSSApower_inN4
N5VDDpower_inN5
N6VSSpassiveN6
N7VDDpower_inN7
N8VSSpassiveN8
N9VDDpower_inN9
P1PWR_LPoutputP1
P2PA13bidirectionalP2
P3PA3bidirectionalP3
P4PA5bidirectionalP4
P5VSSApassiveP5
P6VDDpower_inP6
P7VSSpassiveP7
P8VDDpower_inP8
P9VSSpassiveP9
R1PA14bidirectionalR1
R2VSSpassiveR2
R3PA0bidirectionalR3
R4PA4bidirectionalR4
R5VSSApassiveR5
R6VSSpassiveR6
R7VDDpower_inR7
R8VSSpassiveR8
R9VDDpower_inR9
T1PE2bidirectionalT1
T2PC2bidirectionalT2
T3PC3bidirectionalT3
T4VSSpassiveT4
T5PA6bidirectionalT5
T6PA7bidirectionalT6
T7PC0bidirectionalT7
T8PB5bidirectionalT8
T9PB13bidirectionalT9
U1PG14bidirectionalU1
U2PG13bidirectionalU2
U3VSSpassiveU3
U4PA1bidirectionalU4
U5PF11bidirectionalU5
U6VSSpassiveU6
U7PG8bidirectionalU7
U8VSSpassiveU8
U9PF10bidirectionalU9
V1PB11bidirectionalV1
V2PC1bidirectionalV2
V3PB1bidirectionalV3
V4PC5bidirectionalV4
V5PB12bidirectionalV5
V6PG11bidirectionalV6
V7PG10bidirectionalV7
V8PD11bidirectionalV8
V9PF6bidirectionalV9
W1VSSpassiveW1
W2PA2bidirectionalW2
W3PB0bidirectionalW3
W4PC4bidirectionalW4
W5PB10bidirectionalW5
W6PB8bidirectionalW6
W7PE9bidirectionalW7
W8PF7bidirectionalW8
W9PF9bidirectionalW9
A10PC9bidirectionalA10
A11PC11bidirectionalA11
A12VDD_Unusedpower_inA12
A13DNUno_connectA13
A14DNUno_connectA14
A15DNUno_connectA15
A16VDD1V2_Unusedpower_inA16
A17DDR_DQ0bidirectionalA17
A18DDR_DQ1bidirectionalA18
A19VSSpassiveA19
B10PD2bidirectionalB10
B11PE4bidirectionalB11
B12VDDA1V8_Unusedpower_inB12
B13DNUno_connectB13
B14DNUno_connectB14
B15DNUno_connectB15
B16VDD1V2_Unusedpower_inB16
B17DDR_DQ3bidirectionalB17
B18DDR_DQ7bidirectionalB18
B19DDR_DQS0NbidirectionalB19
C10PC12bidirectionalC10
C11PC8bidirectionalC11
C12VSSpassiveC12
C13VSSpassiveC13
C14VSSpassiveC14
C15VSSpassiveC15
C16VSSpassiveC16
C17VSSpassiveC17
C18DDR_DQM0bidirectionalC18
C19DDR_DQS0PbidirectionalC19
D10PC6bidirectionalD10
D11PC10bidirectionalD11
D12NJTRSTbidirectionalD12
D13JTDIbidirectionalD13
D14JTDObidirectionalD14
D15JTMSbidirectionalD15
D16JTCKbidirectionalD16
D17DDR_DQ5bidirectionalD17
D18DDR_DQ2bidirectionalD18
D19DDR_DQ6bidirectionalD19
E10VSSpassiveE10
E11VDDCOREpower_inE11
E12VSSpassiveE12
E13VDDCOREpower_inE13
E14VSSpassiveE14
E15VDDQ_DDRpower_inE15
E16VSSpassiveE16
E17DDR_A7bidirectionalE17
E18DDR_DQ4bidirectionalE18
F10VDDCOREpower_inF10
F11VSSpassiveF11
F12VDDCOREpower_inF12
F13VSS_PLL2power_inF13
F14VDDQ_DDRpower_inF14
F15VSSpassiveF15
F17DDR_A13bidirectionalF17
F18DDR_ZQbidirectionalF18
F19DDR_A3bidirectionalF19
G10VSSpassiveG10
G11VDDCOREpower_inG11
G12VSSpassiveG12
G13VDD_PLL2power_inG13
G14VSSpassiveG14
G15VDDQ_DDRpower_inG15
G16DDR_RESETNbidirectionalG16
G17DDR_A9bidirectionalG17
G18DDR_A2bidirectionalG18
G19DDR_BA0bidirectionalG19
H10VDDCOREpower_inH10
H11VSSpassiveH11
H12VDDCOREpower_inH12
H13VSSpassiveH13
H14VDDQ_DDRpower_inH14
H15VSSpassiveH15
H17DDR_A5bidirectionalH17
H18DDR_A0bidirectionalH18
H19DDR_ODTbidirectionalH19
J10VSSpassiveJ10
J11VDDCOREpower_inJ11
J12VSSpassiveJ12
J13VDDCOREpower_inJ13
J14VSSpassiveJ14
J15VDDQ_DDRpower_inJ15
J16DDR_BA2bidirectionalJ16
J17DDR_WENbidirectionalJ17
J18DDR_CSNbidirectionalJ18
J19DDR_DTO1bidirectionalJ19
K10VDDCOREpower_inK10
K11VSSpassiveK11
K12VDDCOREpower_inK12
K13VSSpassiveK13
K14VDDQ_DDRpower_inK14
K15VSSpassiveK15
K17DDR_CASNbidirectionalK17
K18DDR_DTO0bidirectionalK18
K19DDR_CLKNbidirectionalK19
L10VSSpassiveL10
L11VDDCOREpower_inL11
L12VSSpassiveL12
L13VDDCOREpower_inL13
L14VSSpassiveL14
L15VDDQ_DDRpower_inL15
L16DDR_A15bidirectionalL16
L17DDR_A12bidirectionalL17
L18DDR_RASNbidirectionalL18
L19DDR_CLKPbidirectionalL19
M10VDDCOREpower_inM10
M11VSSpassiveM11
M12VDDCOREpower_inM12
M13VSSpassiveM13
M14VDDQ_DDRpower_inM14
M15VSSpassiveM15
M17DDR_A1bidirectionalM17
M18DDR_A11bidirectionalM18
M19DDR_A10bidirectionalM19
N10VSSpassiveN10
N11VDDCOREpower_inN11
N12VSSpassiveN12
N13VDDCOREpower_inN13
N14VSSpassiveN14
N15VDDQ_DDRpower_inN15
N16DDR_A6bidirectionalN16
N17DDR_BA1bidirectionalN17
N18DDR_A14bidirectionalN18
N19DDR_ATObidirectionalN19
P10VDDpower_inP10
P11VSSpassiveP11
P12VDDCOREpower_inP12
P13VSSpassiveP13
P14VDDQ_DDRpower_inP14
P15VSSpassiveP15
P17DDR_A4bidirectionalP17
P18DDR_DQ8bidirectionalP18
P19DDR_CKEbidirectionalP19
R10VSSpassiveR10
R11VDDpower_inR11
R12VSSpassiveR12
R13VDDCOREpower_inR13
R14VSSpassiveR14
R15VDDQ_DDRpower_inR15
R16VSSpassiveR16
R17DDR_A8bidirectionalR17
R18DDR_DQ10bidirectionalR18
T10PE7bidirectionalT10
T11PE8bidirectionalT11
T12PB6bidirectionalT12
T13PB2bidirectionalT13
T14PG9bidirectionalT14
T15BYPASS_REG1V8bidirectionalT15
T16PA10bidirectionalT16
T17DDR_DQ9bidirectionalT17
T18DDR_DQ13bidirectionalT18
T19DDR_DQS1NbidirectionalT19
U10PF8bidirectionalU10
U11PD12bidirectionalU11
U12PD13bidirectionalU12
U13VSS_USBHSpower_inU13
U14VSS_USBHSpassiveU14
U15OTG_VBUSbidirectionalU15
U16PA12bidirectionalU16
U17VSSpassiveU17
U18DDR_DQM1bidirectionalU18
U19DDR_DQS1PbidirectionalU19
V10PE10bidirectionalV10
V11VDDA1V8_REGpower_inV11
V12VSS_USBHSpassiveV12
V13USB_DM2bidirectionalV13
V14USB_DP1bidirectionalV14
V15VSS_USBHSpassiveV15
V16USB_RREFbidirectionalV16
V17PA11bidirectionalV17
V18DDR_DQ14bidirectionalV18
V19DDR_DQ11bidirectionalV19
W10PG7bidirectionalW10
W11VDDA1V1_REGpower_inW11
W12VDD3V3_USBHSpower_inW12
W13USB_DP2bidirectionalW13
W14USB_DM1bidirectionalW14
W15VDD3V3_USBFSpower_inW15
W16DDR_VREFbidirectionalW16
W17DDR_DQ15bidirectionalW17
W18DDR_DQ12bidirectionalW18
W19VSSpassiveW19

Provenance

Credit
KiCad Libraries Contributors
Licence
CC-BY-SA-4.0-with-KiCad-exception
Link method
exact
Cross-check
passed