STM32MP157FAAx

MCU_ST_STM32MP1

STMicroelectronics Arm Cortex-A7 MCU, 0KB flash, 708KB RAM, 176 GPIO, LFBGA448

Symbol

448 pins
Schematic symbol for STM32MP157FAAx
Units
1
Kind
part
Grid
on 1.27 mm

Footprint

448 pads
Footprint for STM32MP157FAAx
Library
Package_BGA
Mount
smd
Courtyard
20 × 20 mm
Link
exact

3D model

none
no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

Every pin on the symbol has a pad on the footprint.

PinNameTypePad
A1VSSpower_inA1
A2PH5bidirectionalA2
A3PH4bidirectionalA3
A4PE13bidirectionalA4
A5PK6bidirectionalA5
A6PK4bidirectionalA6
A7PJ13bidirectionalA7
A8PD10bidirectionalA8
A9PD5bidirectionalA9
B1PH10bidirectionalB1
B2VSSpassiveB2
B3PH11bidirectionalB3
B4PE14bidirectionalB4
B5PK7bidirectionalB5
B6PK3bidirectionalB6
B7PJ14bidirectionalB7
B8PJ12bidirectionalB8
B9PF1bidirectionalB9
C1PH15bidirectionalC1
C2PH14bidirectionalC2
C3VSSpassiveC3
C4PE15bidirectionalC4
C5PE0bidirectionalC5
C6PK5bidirectionalC6
C7PJ15bidirectionalC7
C8VSSpassiveC8
C9PD4bidirectionalC9
D1PI0bidirectionalD1
D2PI14bidirectionalD2
D3PH13bidirectionalD3
D4VSSpassiveD4
D5PE11bidirectionalD5
D6PH8bidirectionalD6
D7PE1bidirectionalD7
D8PK0bidirectionalD8
D9PF5bidirectionalD9
E1PI2bidirectionalE1
E2PI1bidirectionalE2
E3PI3bidirectionalE3
E4PE12bidirectionalE4
E5VSSpassiveE5
E6PH9bidirectionalE6
E7PK1bidirectionalE7
E8PK2bidirectionalE8
E9PE6bidirectionalE9
F1PI7bidirectionalF1
F2PI5bidirectionalF2
F3PI15bidirectionalF3
F4PZ3bidirectionalF4
F5PH12bidirectionalF5
F6VSSpassiveF6
F7VSSpassiveF7
F8VSSpassiveF8
F9PF4bidirectionalF9
G1PZ4bidirectionalG1
G2PZ0bidirectionalG2
G3PZ6bidirectionalG3
G4VSSpassiveG4
G5PI6bidirectionalG5
G6VSSpassiveG6
G8VSSpassiveG8
H1PI13bidirectionalH1
H2PI12bidirectionalH2
H3PZ7bidirectionalH3
H4PZ5bidirectionalH4
H5PZ1bidirectionalH5
H6PJ8bidirectionalH6
H7VSSpassiveH7
H9VDDCOREpower_inH9
J1PJ3bidirectionalJ1
J2PJ0bidirectionalJ2
J3PJ10bidirectionalJ3
J4PG12bidirectionalJ4
J5PI9bidirectionalJ5
J6PI4bidirectionalJ6
J8VDDCOREpower_inJ8
J9VSSpassiveJ9
K1PJ5bidirectionalK1
K2PJ4bidirectionalK2
K3VSSpassiveK3
K4PJ2bidirectionalK4
K5PZ2bidirectionalK5
K6PJ11bidirectionalK6
K7VSSpassiveK7
K9VDDCOREpower_inK9
L1PD15bidirectionalL1
L2PJ9bidirectionalL2
L3PD6bidirectionalL3
L4PJ7bidirectionalL4
L5PJ6bidirectionalL5
L6PJ1bidirectionalL6
L8VDDCOREpower_inL8
L9VSSpassiveL9
M1PD8bidirectionalM1
M2PD9bidirectionalM2
M3PD14bidirectionalM3
M4VBATpower_inM4
M5VSS_PLLpower_inM5
M6VDD_PLLpower_inM6
M7VSSpassiveM7
M9VDDpower_inM9
N1PI8bidirectionalN1
N2PC13bidirectionalN2
N3BOOT0inputN3
N4BOOT1inputN4
N5VDD_ANApower_inN5
N6VREF-inputN6
N8VDDpower_inN8
N9VSSpassiveN9
P1PC14bidirectionalP1
P2PC15bidirectionalP2
P3VSSpassiveP3
P4BOOT2inputP4
P5VSS_ANApower_inP5
P6VREF+inputP6
P7VSSpassiveP7
P9VDDpower_inP9
R1NRST_COREinputR1
R2NRSTinputR2
R3PA14bidirectionalR3
R4ANA0bidirectionalR4
R5VDDApower_inR5
R6VSSApower_inR6
R8VSSpassiveR8
T1PH0bidirectionalT1
T2PH1bidirectionalT2
T3PI11bidirectionalT3
T4PA3bidirectionalT4
T5ANA1bidirectionalT5
T6VSSApassiveT6
T7VSSpassiveT7
T9VSSpassiveT9
U1PWR_LPoutputU1
U2PDR_ON_COREbidirectionalU2
U3PC3bidirectionalU3
U4PG3bidirectionalU4
U5PA5bidirectionalU5
U6VSSApassiveU6
U7VSSpassiveU7
U8PG5bidirectionalU8
U9VDDpower_inU9
V1PWR_ONoutputV1
V2PDR_ONbidirectionalV2
V3PF3bidirectionalV3
V4PA1bidirectionalV4
V5VSSpassiveV5
V6PA4bidirectionalV6
V7PF14bidirectionalV7
V8PF12bidirectionalV8
V9PB10bidirectionalV9
W1PI10bidirectionalW1
W2PH7bidirectionalW2
W3PA13bidirectionalW3
W4PG2bidirectionalW4
W5PG0bidirectionalW5
W6PF15bidirectionalW6
W7PF13bidirectionalW7
W8PF11bidirectionalW8
W9PA6bidirectionalW9
Y1PC2bidirectionalY1
Y2PE2bidirectionalY2
Y3VSSpassiveY3
Y4PG1bidirectionalY4
Y5PB11bidirectionalY5
Y6PH3bidirectionalY6
Y7VSSpassiveY7
Y8PG8bidirectionalY8
Y9PA7bidirectionalY9
A10PE3bidirectionalA10
A11PA9bidirectionalA11
A12PB3bidirectionalA12
A13PB14bidirectionalA13
A14VDD_DSIpower_inA14
A15DSIHOST_D0NbidirectionalA15
A16DSIHOST_CKNbidirectionalA16
A17DSIHOST_D1NbidirectionalA17
A18VDD1V2_DSI_PHYpower_inA18
A19VSSpassiveA19
A20DDR_DQ20bidirectionalA20
A21DDR_DQ23bidirectionalA21
A22VSSpassiveA22
AA1PG13bidirectionalAA1
AA2PG14bidirectionalAA2
AA3PA0bidirectionalAA3
AA4VSSpassiveAA4
AA5PB1bidirectionalAA5
AA6PC5bidirectionalAA6
AA7PB12bidirectionalAA7
AA8PB5bidirectionalAA8
AA9PG10bidirectionalAA9
AB1VSSpassiveAB1
AB2PA2bidirectionalAB2
AB3PC1bidirectionalAB3
AB4PG4bidirectionalAB4
AB5PB0bidirectionalAB5
AB6PC4bidirectionalAB6
AB7PH2bidirectionalAB7
AB8PB8bidirectionalAB8
AB9PD11bidirectionalAB9
B10PD1bidirectionalB10
B11PD3bidirectionalB11
B12PB15bidirectionalB12
B13PA8bidirectionalB13
B14VDDA1V8_DSIpower_inB14
B15DSIHOST_D0PbidirectionalB15
B16DSIHOST_CKPbidirectionalB16
B17DSIHOST_D1PbidirectionalB17
B18VDD1V2_DSI_REGpower_inB18
B19VSSpassiveB19
B20DDR_DQ19bidirectionalB20
B21DDR_DQ16bidirectionalB21
B22DDR_DQS2NbidirectionalB22
C10PD0bidirectionalC10
C11VSSpassiveC11
C12PE5bidirectionalC12
C13PB4bidirectionalC13
C14VSS_DSIpower_inC14
C15VSS_DSIpassiveC15
C16VSS_DSIpassiveC16
C17VSS_DSIpassiveC17
C18VSS_DSIpassiveC18
C19VSSpassiveC19
C20VSSpassiveC20
C21DDR_DQS2PbidirectionalC21
C22DDR_DQM2bidirectionalC22
D10PG15bidirectionalD10
D11PG6bidirectionalD11
D12PD2bidirectionalD12
D13PC7bidirectionalD13
D14PC9bidirectionalD14
D15PC11bidirectionalD15
D16JTDIbidirectionalD16
D17JTCKbidirectionalD17
D18VDD_PLL2power_inD18
D19VSS_PLL2power_inD19
D20DDR_DQ22bidirectionalD20
D21DDR_DQ17bidirectionalD21
D22DDR_DQ18bidirectionalD22
E10PF0bidirectionalE10
E11PA15bidirectionalE11
E12PC12bidirectionalE12
E13PC6bidirectionalE13
E14PC8bidirectionalE14
E15NJTRSTbidirectionalE15
E16JTDObidirectionalE16
E17JTMSbidirectionalE17
E18VDDQ_DDRpower_inE18
E19VSSpassiveE19
E20DDR_DQ3bidirectionalE20
E21DDR_DQ0bidirectionalE21
E22DDR_DQ21bidirectionalE22
F10PD7bidirectionalF10
F11PB7bidirectionalF11
F12PB9bidirectionalF12
F13PF2bidirectionalF13
F14PC10bidirectionalF14
F15PE4bidirectionalF15
F16VSSpassiveF16
F17VDDQ_DDRpower_inF17
F18DDR_A7bidirectionalF18
F19DDR_RESETNbidirectionalF19
F20VSSpassiveF20
F21DDR_DQ1bidirectionalF21
G10VSSpassiveG10
G12VSSpassiveG12
G14VSSpassiveG14
G16VDDQ_DDRpower_inG16
G17VSSpassiveG17
G18DDR_A13bidirectionalG18
G19DDR_DQ7bidirectionalG19
G20DDR_DQM0bidirectionalG20
G21DDR_DQS0NbidirectionalG21
G22DDR_DQS0PbidirectionalG22
H11VDDCOREpower_inH11
H13VDDCOREpower_inH13
H15VDDCOREpower_inH15
H17VDDQ_DDRpower_inH17
H18DDR_A9bidirectionalH18
H19DDR_A5bidirectionalH19
H20DDR_DQ5bidirectionalH20
H21DDR_DQ2bidirectionalH21
H22DDR_DQ6bidirectionalH22
J10VDDCOREpower_inJ10
J11VSSpassiveJ11
J12VDDCOREpower_inJ12
J13VSSpassiveJ13
J14VDDCOREpower_inJ14
J16VDDQ_DDRpower_inJ16
J17VSSpassiveJ17
J18DDR_A2bidirectionalJ18
J19DDR_A3bidirectionalJ19
J20VSSpassiveJ20
J21DDR_DQ4bidirectionalJ21
K10VSSpassiveK10
K11VDDCOREpower_inK11
K12VSSpassiveK12
K13VDDCOREpower_inK13
K14VSSpassiveK14
K15VDDCOREpower_inK15
K17VDDQ_DDRpower_inK17
K18DDR_BA2bidirectionalK18
K19DDR_A0bidirectionalK19
K20DDR_BA0bidirectionalK20
K21DDR_DTO1bidirectionalK21
K22DDR_ZQbidirectionalK22
L10VDDCOREpower_inL10
L11VSSpassiveL11
L12VDDCOREpower_inL12
L13VSSpassiveL13
L14VDDCOREpower_inL14
L16VDDQ_DDRpower_inL16
L17VSSpassiveL17
L18DDR_CSNbidirectionalL18
L19VSSpassiveL19
L20VSSpassiveL20
L21DDR_ODTbidirectionalL21
L22DDR_DTO0bidirectionalL22
M10VSSpassiveM10
M11VDDCOREpower_inM11
M12VSSpassiveM12
M13VDDCOREpower_inM13
M14VSSpassiveM14
M15VDDCOREpower_inM15
M17VDDQ_DDRpower_inM17
M18DDR_A1bidirectionalM18
M19DDR_A15bidirectionalM19
M20DDR_RASNbidirectionalM20
M21DDR_WENbidirectionalM21
M22DDR_CASNbidirectionalM22
N10VDDpower_inN10
N11VSSpassiveN11
N12VDDCOREpower_inN12
N13VSSpassiveN13
N14VDDCOREpower_inN14
N16VDDQ_DDRpower_inN16
N17VSSpassiveN17
N18DDR_A10bidirectionalN18
N19DDR_A12bidirectionalN19
N20DDR_CLKPbidirectionalN20
N21DDR_CLKNbidirectionalN21
N22DDR_DQ8bidirectionalN22
P10VSSpassiveP10
P11VDDpower_inP11
P12VSSpassiveP12
P13VDDCOREpower_inP13
P14VSSpassiveP14
P15VDDCOREpower_inP15
P17VDDQ_DDRpower_inP17
P18DDR_A14bidirectionalP18
P19DDR_A11bidirectionalP19
P20VSSpassiveP20
P21DDR_DQ10bidirectionalP21
R10VDDpower_inR10
R12VDDpower_inR12
R14VDDCOREpower_inR14
R16VDDQ_DDRpower_inR16
R17VSSpassiveR17
R18DDR_BA1bidirectionalR18
R19DDR_CKEbidirectionalR19
R20DDR_DQ13bidirectionalR20
R21DDR_DQ9bidirectionalR21
R22DDR_DQS1NbidirectionalR22
T11VSSpassiveT11
T13VDDpower_inT13
T15VDDCOREpower_inT15
T17VDDQ_DDRpower_inT17
T18DDR_A4bidirectionalT18
T19VSSpassiveT19
T20DDR_DQ11bidirectionalT20
T21DDR_DQM1bidirectionalT21
T22DDR_DQS1PbidirectionalT22
U10PC0bidirectionalU10
U11PG11bidirectionalU11
U12VDDpower_inU12
U13VSSpassiveU13
U14VDDpower_inU14
U15VSSpassiveU15
U16VDDQ_DDRpower_inU16
U17VSSpassiveU17
U18DDR_A8bidirectionalU18
U19DDR_A6bidirectionalU19
U20VSSpassiveU20
U21DDR_DQ14bidirectionalU21
V10PB13bidirectionalV10
V11PH6bidirectionalV11
V12PF10bidirectionalV12
V13PB2bidirectionalV13
V14PD13bidirectionalV14
V15OTG_VBUSbidirectionalV15
V16VSSpassiveV16
V17VDDQ_DDRpower_inV17
V18VSSpassiveV18
V19VSSpassiveV19
V20DDR_DQ12bidirectionalV20
V21DDR_DQ15bidirectionalV21
V22DDR_DQ24bidirectionalV22
W10PE7bidirectionalW10
W11PE9bidirectionalW11
W12PD12bidirectionalW12
W13PB6bidirectionalW13
W14PE10bidirectionalW14
W15PG9bidirectionalW15
W16PA12bidirectionalW16
W17VSSpassiveW17
W18VDDQ_DDRpower_inW18
W19VSSpassiveW19
W20DDR_DQ25bidirectionalW20
W21DDR_DQ31bidirectionalW21
W22DDR_DQ30bidirectionalW22
Y10VSSpassiveY10
Y11PG7bidirectionalY11
Y12PE8bidirectionalY12
Y13VSS_USBHSpower_inY13
Y14VSS_USBHSpassiveY14
Y15VSS_USBHSpassiveY15
Y16PA11bidirectionalY16
Y17PA10bidirectionalY17
Y18VSSpassiveY18
Y19VDDQ_DDRpower_inY19
Y20VSSpassiveY20
Y21DDR_DQS3PbidirectionalY21
Y22DDR_DQS3NbidirectionalY22
AA10PF7bidirectionalAA10
AA11PF6bidirectionalAA11
AA12BYPASS_REG1V8bidirectionalAA12
AA13VSS_USBHSpassiveAA13
AA14USB_DM2bidirectionalAA14
AA15USB_DP1bidirectionalAA15
AA16VSS_USBHSpassiveAA16
AA17USB_RREFbidirectionalAA17
AA18VSSpassiveAA18
AA19DDR_ATObidirectionalAA19
AA20DDR_DQ29bidirectionalAA20
AA21DDR_DQ28bidirectionalAA21
AA22DDR_DQM3bidirectionalAA22
AB10PF8bidirectionalAB10
AB11PF9bidirectionalAB11
AB12VDDA1V8_REGpower_inAB12
AB13VDD3V3_USBHSpower_inAB13
AB14USB_DP2bidirectionalAB14
AB15USB_DM1bidirectionalAB15
AB16VDD3V3_USBFSpower_inAB16
AB17VDDA1V1_REGpower_inAB17
AB18VSSpassiveAB18
AB19DDR_VREFbidirectionalAB19
AB20DDR_DQ27bidirectionalAB20
AB21DDR_DQ26bidirectionalAB21
AB22VSSpassiveAB22

Provenance

Credit
KiCad Libraries Contributors
Licence
CC-BY-SA-4.0-with-KiCad-exception
Link method
exact
Cross-check
passed