FU540-C000

MCU_SiFive

64-bit RISC‑V SoC, BGA-484

Symbol

484 pins
Schematic symbol for FU540-C000
Units
6
Kind
part
Grid
on 1.27 mm

Footprint

484 pads
Footprint for FU540-C000
Library
Package_BGA
Mount
smd
Courtyard
25 × 25 mm
Link
exact
Footprint page
Open →

3D model

STEP

Package_BGA_BGA-484_23.0x23.0mm_Layout22x22_P1.0mm

23 × 23 × 2.32 mm

489 KB STEP

Library
Package_BGA_BGA-484_23.0x23.0mm_Layout22x22
Link
exact
Model page
Open →

Pins and pads

Every pin on the symbol has a pad on the footprint.

PinNameTypePad
A1VSSpower_inA1
A2VSSpassiveA2
A3VSSpassiveA3
A4DDR_MEM_D[18]bidirectionalA4
A5DDR_MEM_D[19]bidirectionalA5
A6DDR_MEM_DQS_P[2]bidirectionalA6
A7DDR_MEM_DQS_M[2]bidirectionalA7
A8GEMGXL_0_RXD_5inputA8
A9VSSpassiveA9
B1DDR_MEM_D[1]bidirectionalB1
B2DDR_MEM_D[17]bidirectionalB2
B3DDR_MEM_D[22]bidirectionalB3
B4DDR_MEM_D[16]bidirectionalB4
B5DDR_MEM_D[20]bidirectionalB5
B6DDR_MEM_D[23]bidirectionalB6
B7GEMGXL_0_TX_ENoutputB7
B8GEMGXL_0_TXD_6outputB8
B9VDDpassiveB9
C1DDR_MEM_D[4]bidirectionalC1
C2DDR_MEM_D[29]bidirectionalC2
C3DDR_MEM_D[27]bidirectionalC3
C4DDR_MEM_D[24]bidirectionalC4
C5DDR_MEM_D[21]bidirectionalC5
C6DDR_MEM_DM[2]bidirectionalC6
C7DDR_MEM_D[31]bidirectionalC7
C8GEMGXL_0_TX_CLKinputC8
C9GEMGXL_0_RXD_6inputC9
D1VSSpassiveD1
D2DDR_MEM_D[0]bidirectionalD2
D3DDR_MEM_D[30]bidirectionalD3
D4DDR_MEM_D[25]bidirectionalD4
D5DDR_MEM_DM[3]bidirectionalD5
D6DDR_MEM_D[26]bidirectionalD6
D7DDR_MEM_DQS_M[3]bidirectionalD7
D8DDR_RSVD1passiveD8
D9GEMGXL_0_TXD_7outputD9
E1DDR_MEM_D[6]bidirectionalE1
E2DDR_MEM_D[3]bidirectionalE2
E3VDDpassiveE3
E4VSSpassiveE4
E5DDR_MEM_DM[0]bidirectionalE5
E6DDR_MEM_D[28]bidirectionalE6
E7DDR_MEM_DQS_P[3]bidirectionalE7
E8DDR_RSVD0passiveE8
E9GEMGXL_0_RXD_7inputE9
F1DDR_MEM_D[9]bidirectionalF1
F2DDR_MEM_DQS_P[0]bidirectionalF2
F3DDR_MEM_DQS_M[0]bidirectionalF3
F4DDR_MEM_D[2]bidirectionalF4
F5DDR_MEM_D[10]bidirectionalF5
F6DDR_CAL_0passiveF6
F7VSSpassiveF7
F8DDR_RSVD2passiveF8
F9DDR_RSVD3passiveF9
G1DDR_MEM_D[11]bidirectionalG1
G2VSSpassiveG2
G3DDR_MEM_D[7]bidirectionalG3
G4DDR_MEM_D[5]bidirectionalG4
G5DDR_MEM_DM[1]bidirectionalG5
G6VSSpassiveG6
G7DDR_VDDQpower_inG7
G8VSSpassiveG8
G9VDDpassiveG9
H1DDR_MEM_D[12]bidirectionalH1
H2DDR_MEM_DQS_P[1]bidirectionalH2
H3DDR_MEM_DQS_M[1]bidirectionalH3
H4DDR_MEM_D[8]bidirectionalH4
H5DDR_MEM_ECC_D[0]bidirectionalH5
H6DDR_VDDQpassiveH6
H7VSSpassiveH7
H8VDDpassiveH8
H9VSSpassiveH9
J1VSSpassiveJ1
J2DDR_MEM_D[14]bidirectionalJ2
J3DDR_MEM_D[13]bidirectionalJ3
J4DDR_MEM_D[15]bidirectionalJ4
J5DDR_MEM_ECC_DMbidirectionalJ5
J6VSSpassiveJ6
J7DDR_VDDQpassiveJ7
J8VSSpassiveJ8
J9VDDpassiveJ9
K1DDR_MEM_ECC_D[1]bidirectionalK1
K2DDR_MEM_ECC_DQS_PbidirectionalK2
K3DDR_MEM_ECC_DQS_MbidirectionalK3
K4DDR_MEM_ECC_D[2]bidirectionalK4
K5DDR_MEM_CLKoutputK5
K6DDR_VDDQpassiveK6
K7VSSpassiveK7
K8VDDpassiveK8
K9VSSpassiveK9
L1DDR_MEM_ECC_D[4]bidirectionalL1
L2DDR_MEM_ECC_D[3]bidirectionalL2
L3DDR_MEM_ECC_D[7]bidirectionalL3
L4DDR_MEM_ECC_D[5]bidirectionalL4
L5DDR_MEM_CLK_NoutputL5
L6VSSpassiveL6
L7DDR_VDDQpassiveL7
L8VSSpassiveL8
L9DDR_VDDPLLpassiveL9
M1DDR_MEM_ECC_D[6]bidirectionalM1
M2DDR_MEM_RAS_NoutputM2
M3DDR_MEM_CAS_NoutputM3
M4DDR_MEM_BANK[0]outputM4
M5DDR_MEM_BANK[2]outputM5
M6DDR_VDDQpassiveM6
M7VSSpassiveM7
M8VDDpassiveM8
M9DDR_VDDPLLpower_inM9
N1DDR_MEM_WE_NoutputN1
N2DDR_MEM_BANK[1]outputN2
N3DDR_MEM_ADDR[0]outputN3
N4DDR_MEM_ADDR[2]outputN4
N5DDR_MEM_ADDR[5]outputN5
N6VSSpassiveN6
N7DDR_VDDQpassiveN7
N8VSSpassiveN8
N9VDDpassiveN9
P1VSSpassiveP1
P2VDDpassiveP2
P3DDR_MEM_ADDR[3]outputP3
P4DDR_MEM_ADDR[6]outputP4
P5DDR_MEM_ADDR[12]outputP5
P6DDR_VDDQpassiveP6
P7VSSpassiveP7
P8VDDpassiveP8
P9VSSpassiveP9
R1DDR_MEM_ADDR[1]outputR1
R2DDR_MEM_ADDR[7]outputR2
R3DDR_MEM_ADDR[8]outputR3
R4DDR_MEM_ADDR[11]outputR4
R5DDR_MEM_D[32]bidirectionalR5
R6VSSpassiveR6
R7DDR_VDDQpassiveR7
R8VSSpassiveR8
R9VDDpassiveR9
T1DDR_MEM_ADDR[4]outputT1
T2DDR_MEM_ADDR[13]outputT2
T3DDR_MEM_ADDR[9]outputT3
T4DDR_MEM_D[34]bidirectionalT4
T5DDR_MEM_DM[4]bidirectionalT5
T6DDR_VDDQpassiveT6
T7VSSpassiveT7
T8VDDpassiveT8
T9VSSpassiveT9
U1DDR_MEM_ADDR[10]outputU1
U2DDR_MEM_PARITY_INoutputU2
U3DDR_MEM_ADDR[14]outputU3
U4DDR_MEM_DQS_M[4]bidirectionalU4
U5DDR_MEM_D[39]bidirectionalU5
U6VSSpassiveU6
U7DDR_VDDQCKpower_inU7
U8VSSpassiveU8
U9VDDpassiveU9
V1VSSpassiveV1
V2DDR_MEM_D[35]bidirectionalV2
V3DDR_MEM_ADDR[15]outputV3
V4DDR_MEM_DQS_P[4]bidirectionalV4
V5DDR_MEM_D[40]bidirectionalV5
V6VDDpassiveV6
V7VSSpassiveV7
V8VDDpassiveV8
V9VSSpassiveV9
W1DDR_MEM_D[33]bidirectionalW1
W2DDR_MEM_D[38]bidirectionalW2
W3DDR_MEM_D[37]bidirectionalW3
W4DDR_MEM_DQS_M[5]bidirectionalW4
W5DDR_MEM_DM[5]bidirectionalW5
W6DDR_MEM_ERROR_NinputW6
W7DDR_MEM_CS_N[1]outputW7
W8DDR_MEM_D[51]bidirectionalW8
W9DDR_MEM_D[55]bidirectionalW9
Y1DDR_MEM_D[36]bidirectionalY1
Y2DDR_MEM_D[43]bidirectionalY2
Y3DDR_MEM_D[42]bidirectionalY3
Y4DDR_MEM_DQS_P[5]bidirectionalY4
Y5DDR_MEM_RESET_NoutputY5
Y6DDR_MEM_CS_N[0]outputY6
Y7DDR_MEM_DQS_P[6]bidirectionalY7
Y8DDR_MEM_DQS_M[7]bidirectionalY8
Y9DDR_MEM_D[53]bidirectionalY9
A10GEMGXL_0_RXD_2inputA10
A11GEMGXL_0_RX_DVinputA11
A12GEMGXL_0_RXD_0inputA12
A13GEMGXL_0_COLinputA13
A14VSSpassiveA14
A15HFXOSCINpassiveA15
A16PRCI_RSVD0passiveA16
A17PRCI_PORESET_NinputA17
A18VSSpassiveA18
A19MSEL_MSEL_0inputA19
A20MSEL_MSEL_2inputA20
A21GPIO_0_P_9bidirectionalA21
A22VSSpassiveA22
AA1DDR_MEM_D[41]bidirectionalAA1
AA2VSSpassiveAA2
AA3DDR_MEM_D[45]bidirectionalAA3
AA4DDR_MEM_D[47]bidirectionalAA4
AA5DDR_MEM_ODT[0]outputAA5
AA6DDR_MEM_CKE[1]outputAA6
AA7DDR_MEM_DQS_M[6]bidirectionalAA7
AA8DDR_MEM_DQS_P[7]bidirectionalAA8
AA9DDR_MEM_D[62]bidirectionalAA9
AB1VSSpassiveAB1
AB2DDR_MEM_D[44]bidirectionalAB2
AB3DDR_MEM_D[46]bidirectionalAB3
AB4VSSpassiveAB4
AB5DDR_MEM_ODT[1]outputAB5
AB6DDR_MEM_CKE[0]outputAB6
AB7VSSpassiveAB7
AB8DDR_MEM_D[57]bidirectionalAB8
AB9DDR_MEM_D[59]bidirectionalAB9
B10GEMGXL_0_RXD_1inputB10
B11GEMGXL_0_RX_ERinputB11
B12GEMGXL_0_TXD_0outputB12
B13GEMGXL_0_MDCoutputB13
B14VDDpassiveB14
B15HFXOSCOUTpassiveB15
B16PRCI_RTCXALTCLKINpassiveB16
B17PRCI_RSVD6passiveB17
B18VDDpassiveB18
B19MSEL_MSEL_3inputB19
B20GPIO_0_P_11bidirectionalB20
B21GPIO_0_P_12bidirectionalB21
B22GPIO_0_P_14bidirectionalB22
C10GEMGXL_0_TXD_4outputC10
C11GEMGXL_0_TXD_1outputC11
C12GEMGXL_0_MDIObidirectionalC12
C13GEMGXL_0_CRSinputC13
C14PRCI_RSVD15passiveC14
C15PRCI_HFXSELinputC15
C16PRCI_RSVD4passiveC16
C17PRCI_ERESET_NinputC17
C18MSEL_MSEL_1inputC18
C19JTAG_TDIinputC19
C20GPIO_0_P_7bidirectionalC20
C21GPIO_0_P_2bidirectionalC21
C22GPIO_0_P_1bidirectionalC22
D10GEMGXL_0_TXD_5outputD10
D11GEMGXL_0_TXD_2outputD11
D12VSSpassiveD12
D13PRCI_RSVD1passiveD13
D14PRCI_RSVD11passiveD14
D15PRCI_RTCXSELinputD15
D16PRCI_RSVD3passiveD16
D17PRCI_RSVD10passiveD17
D18JTAG_TCKinputD18
D19GPIO_0_P_8bidirectionalD19
D20GPIO_0_P_5bidirectionalD20
D21GPIO_0_P_3bidirectionalD21
D22PWM_1_P_0bidirectionalD22
E10GEMGXL_0_RXD_4inputE10
E11GEMGXL_0_RXD_3inputE11
E12GEMGXL_0_GTX_CLKinputE12
E13PRCI_RSVD2passiveE13
E14PRCI_RSVD12passiveE14
E15PRCI_RSVD5passiveE15
E16PRCI_RSVD9passiveE16
E17JTAG_TDOoutputE17
E18GPIO_0_P_4bidirectionalE18
E19GPIO_0_P_13bidirectionalE19
E20GPIO_0_P_6bidirectionalE20
E21VDDpassiveE21
E22VSSpassiveE22
F10GEMGXL_0_TX_ERoutputF10
F11GEMGXL_0_TXD_3outputF11
F12GEMGXL_0_RX_CLKinputF12
F13PRCI_RSVD14passiveF13
F14PRCI_RSVD13passiveF14
F15PRCI_HFXCLKINinputF15
F16JTAG_TMSinputF16
F17GPIO_0_P_0bidirectionalF17
F18GPIO_0_P_10bidirectionalF18
F19PWM_1_P_3bidirectionalF19
F20PWM_0_P_2bidirectionalF20
F21PWM_0_P_1bidirectionalF21
F22QSPI_1_DQ_2bidirectionalF22
G10VSSpassiveG10
G11VDDpassiveG11
G12VSSpassiveG12
G13PRCI_RSVD7passiveG13
G14OTP_VDDpower_inG14
G15VDDpassiveG15
G16VSSpassiveG16
G17GPIO_0_P_15bidirectionalG17
G18PWM_1_P_2bidirectionalG18
G19PWM_0_P_0bidirectionalG19
G20PWM_0_P_3bidirectionalG20
G21QSPI_1_CS_1outputG21
G22QSPI_1_DQ_0bidirectionalG22
H10VDDpassiveH10
H11GIVSSpower_inH11
H12VDDpassiveH12
H13PRCI_RSVD8passiveH13
H14VDDpassiveH14
H15VSSpassiveH15
H16VDDpassiveH16
H17PWM_1_P_1bidirectionalH17
H18QSPI_1_SCKoutputH18
H19QSPI_1_CS_2outputH19
H20QSPI_0_DQ_3bidirectionalH20
H21QSPI_0_DQ_0bidirectionalH21
H22QSPI_0_DQ_1bidirectionalH22
J10VSSpassiveJ10
J11GIVDDpower_inJ11
J12GEMGXLPLL_AVSSpower_inJ12
J13DDRPLL_AVSSpower_inJ13
J14COREPLL_AVSSpower_inJ14
J15VDDpassiveJ15
J16VSSpassiveJ16
J17QSPI_1_DQ_3bidirectionalJ17
J18QSPI_1_DQ_1bidirectionalJ18
J19QSPI_0_CS_0outputJ19
J20QSPI_1_CS_3outputJ20
J21QSPI_0_DQ_2bidirectionalJ21
J22VSSpassiveJ22
K10VDDpassiveK10
K11VSSpassiveK11
K12GEMGXLPLL_AVDDpower_inK12
K13DDRPLL_AVDDpower_inK13
K14COREPLL_AVDDpower_inK14
K15IVSSpower_inK15
K16IVDDpower_inK16
K17QSPI_1_CS_0outputK17
K18QSPI_0_SCKoutputK18
K19CL_0_C2B_D_28outputK19
K20CL_0_C2B_D_24outputK20
K21VDDpassiveK21
K22CL_0_C2B_D_26outputK22
L10VSSpassiveL10
L11VDDpassiveL11
L12VSSpassiveL12
L13VDDpassiveL13
L14VSSpassiveL14
L15IVSSpassiveL15
L16IVDDpassiveL16
L17CL_0_C2B_D_31outputL17
L18CL_0_C2B_D_30outputL18
L19CL_0_C2B_D_27outputL19
L20CL_0_C2B_D_20outputL20
L21CL_0_C2B_D_18outputL21
L22CL_0_C2B_D_29outputL22
M10VDDpassiveM10
M11VSSpassiveM11
M12VDDpassiveM12
M13VSSpassiveM13
M14VDDpassiveM14
M15IVSSpassiveM15
M16IVDDpassiveM16
M17CL_0_C2B_D_15outputM17
M18CL_0_C2B_D_19outputM18
M19CL_0_C2B_D_23outputM19
M20CL_0_C2B_D_12outputM20
M21CL_0_C2B_D_25outputM21
M22CL_0_C2B_D_22outputM22
N10VSSpassiveN10
N11VDDpassiveN11
N12VSSpassiveN12
N13VDDpassiveN13
N14VSSpassiveN14
N15IVSSpassiveN15
N16IVDDpassiveN16
N17CL_0_C2B_SENDoutputN17
N18CL_0_C2B_D_2outputN18
N19CL_0_C2B_D_6outputN19
N20CL_0_C2B_D_21outputN20
N21CL_0_C2B_D_16outputN21
N22CL_0_C2B_D_14outputN22
P10VDDpassiveP10
P11VSSpassiveP11
P12VDDpassiveP12
P13VSSpassiveP13
P14VDDpassiveP14
P15VSSpassiveP15
P16VDDpassiveP16
P17CL_0_B2C_RSTinputP17
P18CL_0_B2C_D_21inputP18
P19CL_0_C2B_CLKoutputP19
P20CL_0_C2B_D_4outputP20
P21VDDpassiveP21
P22VSSpassiveP22
R10VSSpassiveR10
R11VDDpassiveR11
R12VSSpassiveR12
R13VDDpassiveR13
R14VSSpassiveR14
R15VDDpassiveR15
R16VSSpassiveR16
R17CL_0_B2C_D_24inputR17
R18CL_0_B2C_D_17inputR18
R19CL_0_C2B_D_1outputR19
R20CL_0_C2B_D_3outputR20
R21CL_0_C2B_D_8outputR21
R22CL_0_C2B_D_17outputR22
T10VDDpassiveT10
T11VSSpassiveT11
T12VDDpassiveT12
T13VSSpassiveT13
T14VDDpassiveT14
T15VSSpassiveT15
T16VDDpassiveT16
T17VSSpassiveT17
T18CL_0_B2C_D_19inputT18
T19CL_0_C2B_D_0outputT19
T20CL_0_C2B_RSToutputT20
T21CL_0_C2B_D_13outputT21
T22CL_0_C2B_D_10outputT22
U10VSSpassiveU10
U11VDDpassiveU11
U12VSSpassiveU12
U13VDDpassiveU13
U14VSSpassiveU14
U15VDDpassiveU15
U16VSSpassiveU16
U17CL_0_B2C_D_20inputU17
U18CL_0_B2C_D_14inputU18
U19CL_0_B2C_D_18inputU19
U20CL_0_C2B_D_5outputU20
U21CL_0_C2B_D_11outputU21
U22CL_0_C2B_D_7outputU22
V10VDDpassiveV10
V11VSSpassiveV11
V12VDDpassiveV12
V13VSSpassiveV13
V14VDDpassiveV14
V15VSSpassiveV15
V16CL_0_B2C_D_12inputV16
V17CL_0_B2C_D_16inputV17
V18CL_0_B2C_D_9inputV18
V19CL_0_B2C_D_15inputV19
V20CL_0_B2C_D_25inputV20
V21VDDpassiveV21
V22VSSpassiveV22
W10DDR_MEM_DM[6]bidirectionalW10
W11DDR_MEM_D[49]bidirectionalW11
W12DDR_MEM_D[54]bidirectionalW12
W13I2C_0_SDAbidirectionalW13
W14UART_0_RXDinputW14
W15QSPI_2_SCKoutputW15
W16CL_0_B2C_D_4inputW16
W17CL_0_B2C_D_3inputW17
W18CL_0_B2C_D_5inputW18
W19CL_0_B2C_D_11inputW19
W20CL_0_B2C_D_28inputW20
W21CL_0_B2C_SENDinputW21
W22CL_0_C2B_D_9outputW22
Y10DDR_MEM_D[52]bidirectionalY10
Y11DDR_MEM_D[50]bidirectionalY11
Y12DDR_MEM_D[48]bidirectionalY12
Y13UART_0_TXDoutputY13
Y14I2C_0_SCLbidirectionalY14
Y15QSPI_2_DQ_3bidirectionalY15
Y16CL_0_B2C_D_0inputY16
Y17CL_0_B2C_D_7inputY17
Y18CL_0_B2C_D_6inputY18
Y19CL_0_B2C_D_10inputY19
Y20CL_0_B2C_D_27inputY20
Y21CL_0_B2C_D_31inputY21
Y22CL_0_B2C_D_30inputY22
AA10DDR_MEM_D[61]bidirectionalAA10
AA11DDR_MEM_D[63]bidirectionalAA11
AA12DDR_MEM_D[58]bidirectionalAA12
AA13DDR_MEM_D[56]bidirectionalAA13
AA14UART_1_RXDinputAA14
AA15UART_1_TXDoutputAA15
AA16QSPI_2_DQ_0bidirectionalAA16
AA17VDDpower_inAA17
AA18CL_0_B2C_D_2inputAA18
AA19CL_0_B2C_D_8inputAA19
AA20CL_0_B2C_D_23inputAA20
AA21CL_0_B2C_D_29inputAA21
AA22CL_0_B2C_CLKinputAA22
AB10VSSpassiveAB10
AB11DDR_MEM_D[60]bidirectionalAB11
AB12DDR_MEM_DM[7]bidirectionalAB12
AB13VSSpassiveAB13
AB14QSPI_2_CS_0outputAB14
AB15QSPI_2_DQ_1bidirectionalAB15
AB16QSPI_2_DQ_2bidirectionalAB16
AB17VSSpassiveAB17
AB18CL_0_B2C_D_1inputAB18
AB19CL_0_B2C_D_13inputAB19
AB20CL_0_B2C_D_22inputAB20
AB21CL_0_B2C_D_26inputAB21
AB22VSSpassiveAB22

On real boards

1 design use this part

1 carries its footprint on a board, and no other part in the catalog uses that footprint. Largest first.

Provenance

Credit
KiCad Libraries Contributors
Licence
CC-BY-SA-4.0-with-KiCad-exception
Link method
exact
Cross-check
passed