MT40A512M16LY

Memory_RAM

512M x 16-bit (8 Gbit) CMOS Double Data Rate IV Synchronous RAM, Rev. D / E / H, FBGA-96

Symbol

96 pins
Schematic symbol for MT40A512M16LY
Units
1
Kind
part
Grid
on 1.27 mm
Extends
MT40A512M16JY

Footprint

96 pads
Footprint for MT40A512M16LY
Library
Package_BGA
Mount
smd
Courtyard
9.5 × 15.5 mm
Link
exact

3D model

none
no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

Every pin on the symbol has a pad on the footprint.

PinNameTypePad
A1V_{DDQ}power_inA1
A2V_{SSQ}power_inA2
A3DQ8bidirectionalA3
A7UDQS_cbidirectionalA7
A8V_{SSQ}passiveA8
A9V_{DDQ}passiveA9
B1V_{PP}power_inB1
B2V_{SS}power_inB2
B3V_{DD}passiveB3
B7UDQS_tbidirectionalB7
B8DQ9bidirectionalB8
B9V_{DD}power_inB9
C1V_{DDQ}passiveC1
C2DQ12bidirectionalC2
C3DQ10bidirectionalC3
C7DQ11bidirectionalC7
C8DQ13bidirectionalC8
C9V_{SSQ}passiveC9
D1V_{DD}passiveD1
D2V_{SSQ}passiveD2
D3DQ14bidirectionalD3
D7DQ15bidirectionalD7
D8V_{SSQ}passiveD8
D9V_{DDQ}passiveD9
E1V_{SS}passiveE1
E2NF/~{UDM}/~{UDBI}bidirectionalE2
E3V_{SSQ}passiveE3
E7NF/~{LDM}/~{LDBI}bidirectionalE7
E8V_{SSQ}passiveE8
E9V_{SS}passiveE9
F1V_{SSQ}passiveF1
F2V_{DDQ}passiveF2
F3LDQS_cbidirectionalF3
F7DQ1bidirectionalF7
F8V_{DDQ}passiveF8
F9ZQpassiveF9
G1V_{DDQ}passiveG1
G2DQ0bidirectionalG2
G3LDQS_tbidirectionalG3
G7V_{DD}passiveG7
G8V_{SS}passiveG8
G9V_{DDQ}passiveG9
H1V_{SSQ}passiveH1
H2DQ4bidirectionalH2
H3DQ2bidirectionalH3
H7DQ3bidirectionalH7
H8DQ5bidirectionalH8
H9V_{SSQ}passiveH9
J1V_{DD}passiveJ1
J2V_{DDQ}passiveJ2
J3DQ6bidirectionalJ3
J7DQ7bidirectionalJ7
J8V_{DDQ}passiveJ8
J9V_{DD}passiveJ9
K1V_{SS}passiveK1
K2CKEinputK2
K3ODTinputK3
K7CK_tinputK7
K8CK_cinputK8
K9V_{SS}passiveK9
L1V_{DD}passiveL1
L2A14/~{WE}inputL2
L3~{ACT}inputL3
L7~{CS}inputL7
L8A16/~{RAS}inputL8
L9V_{DD}passiveL9
M1V_{REFCA}passiveM1
M2BG0inputM2
M3A10/APinputM3
M7A12/~{BC}inputM7
M8A15/~{CAS}inputM8
M9V_{SS}passiveM9
N1V_{SS}passiveN1
N2BA0inputN2
N3A4inputN3
N7A3inputN7
N8BA1inputN8
N9TENinputN9
P1~{RESET}inputP1
P2A6inputP2
P3A0inputP3
P7A1inputP7
P8A5inputP8
P9~{ALERT}open_collectorP9
R1V_{DD}passiveR1
R2A8inputR2
R3A2inputR3
R7A9inputR7
R8A7inputR8
R9V_{PP}passiveR9
T1V_{SS}passiveT1
T2A11inputT2
T3PARinputT3
T7NF/NCno_connectT7
T8A13inputT8
T9V_{DD}passiveT9

Provenance

Credit
KiCad Libraries Contributors
Licence
CC-BY-SA-4.0-with-KiCad-exception
Link method
exact
Cross-check
passed