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NXP K32L2A41VLL1A

celestial-altium-ARM_Cortex

Symbol

100 pins
Schematic symbol for NXP K32L2A41VLL1A
Units
4
Kind
part
Grid
on 1.27 mm

Footprint

none
no footprint linked

This symbol carries no usable footprint reference, so nothing is linked. Generating one is a better answer than guessing.

3D model

none
no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

No footprint is linked, so there is nothing to cross-check.

PinNameType
1ADC0_SE16/PTE0/RTC_CLKOUT/LPSPI1_SIN/LPUART1_TX/CMP0_OUT/LPI2C1_SDApassive
2ADC0_SE17/PTE1/LLWU_P0/LPSPI1_SOUT/LPUART1_RX/LPI2C1_SCLpassive
3~{ADC0_SE18}/PTE2/LLWU_P1/LPSPI1_SCK/~{LPUART1_CTS_b}/LPI2C1_SDASpassive
4~{ADC0_SE19}/PTE3/LPSPI1_SIN/~{LPUART1_RTS_b}/LPI2C1_SCLSpassive
5PTE4/LLWU_P2/LPSPI1_PCS0passive
6PTE5/LPSPI1_PCS1passive
7PTE6/LLWU_P16/LPSPI1_PCS2/USB_SOF_OUTpassive
8VDD8passive
9VSS9passive
10USB0_DPpassive
11USB0_DMpassive
12VOUT33passive
13VREGINpassive
14ADC0_DP1/ADC0_SE1/PTE16/LPSPI0_PCS0/LPUART2_TX/TPM0_CLKIN/LPSPI1_PCS3/FXIO0_D0passive
15ADC0_DM1/ADC0_SE5a/PTE17/LLWU_P19/LPSPI0_SCK/LPUART2_RX/TPM1_CLKIN/LPTMR0_ALT3/LPTMR1_ALT3/FXIO0_D1passive
16~{ADC0_DP2}/ADC0_SE2/PTE18/LLWU_P20/LPSPI0_SOUT/~{LPUART2_CTS_b}/LPI2C0_SDA/FXIO0_D2passive
17~{ADC0_DM2}/ADC0_SE6a/PTE19/LPSPI0_SIN/~{LPUART2_RTS_b}/LPI2C0_SCL/FXIO0_D3passive
18ADC0_DP0/ADC0_SE0/PTE20/LPSPI2_SCK/TPM1_CH0/LPUART0_TX/FXIO0_D4passive
19ADC0_DM0/ADC0_SE4a/PTE21/LPSPI2_SOUT/TPM1_CH1/LPUART0_RX/FXIO0_D5passive
20ADC0_DP3/ADC0_SE3/PTE22/LPSPI2_SIN/TPM2_CH0/LPUART2_TX/FXIO0_D6passive
21ADC0_DM3/ADC0_SE7a/PTE23/LPSPI2_PCS0/TPM2_CH1/LPUART2_RX/FXIO0_D7passive
22VDDApassive
23VREFH/VREF_OUTpassive
24VREFLpassive
25VSSApassive
26CMP1_IN5/CMP0_IN5/ADC0_SE4b/PTE29/EMVSIM0_CLK/TPM0_CH2/TPM0_CLKINpassive
27DAC0_OUT/CMP1_IN3/ADC0_SE23/CMP0_IN4/PTE30/EMVSIM0_RST/TPM0_CH3/TPM1_CLKINpassive
28PTE31/EMVSIM0_VCCEN/TPM0_CH4/TPM2_CLKIN/LPI2C0_HREQpassive
29VSS29passive
30VDD30passive
31ADC0_SE20/PTE24/EMVSIM0_IO/TPM0_CH0/LPI2C0_SCLpassive
32ADC0_SE21/PTE25/LLWU_P21/EMVSIM0_PD/TPM0_CH1/LPI2C0_SDApassive
33PTE26/RTC_CLKOUT/TPM0_CH5/LPI2C0_SCLS/USB_CLKINpassive
34~{TSI0_CH1}/PTA0/~{LPUART0_CTS_b}/TPM0_CH5/LPI2C0_SDAS/SWD_CLKpassive
35TSI0_CH2/PTA1/LPUART0_RX/TPM2_CH0passive
36TSI0_CH3/PTA2/LPUART0_TX/TPM2_CH1passive
37~{TSI0_CH4}/PTA3/LPI2C1_SCL/TPM0_CH0/~{LPUART0_RTS_b}/SWD_DIOpassive
38~{TSI0_CH5}/PTA4/LLWU_P3/LPI2C1_SDA/TPM0_CH1/~{NMI0_b}passive
39PTA5/USB_CLKIN/TPM0_CH2/LPI2C2_HREQpassive
40PTA6/TPM0_CH3passive
41PTA7/LPSPI0_PCS3/TPM0_CH4/LPI2C2_SDASpassive
42PTA12/TPM1_CH0/LPI2C2_SCLpassive
43PTA13/LLWU_P4/TPM1_CH1/LPI2C2_SDApassive
44PTA14/LPSPI0_PCS0/LPUART0_TX/LPI2C2_SCLpassive
45PTA15/LPSPI0_SCK/LPUART0_RXpassive
46~{PTA16}/LPSPI0_SOUT/~{LPUART0_CTS_b}passive
47~{ADC0_SE22}/PTA17/LPSPI0_SIN/~{LPUART0_RTS_b}passive
48VDD48passive
49VSS49passive
50EXTAL0/PTA18/LPUART1_RX/TPM0_CLKINpassive
51XTAL0/PTA19/LPUART1_TX/TPM1_CLKIN/LPTMR0_ALT1/LPTMR1_ALT1passive
52~{PTA20}/LPI2C0_SCLS/TPM2_CLKIN/~{RESET_b}passive
53ADC0_SE8/TSI0_CH0/PTB0/LLWU_P5/LPI2C0_SCL/TPM1_CH0/FXIO0_D8passive
54ADC0_SE9/TSI0_CH6/PTB1/LPI2C0_SDA/TPM1_CH1/FXIO0_D9passive
55~{ADC0_SE12}/TSI0_CH7/PTB2/LPI2C0_SCL/TPM2_CH0/~{LPUART0_RTS_b}/FXIO0_D10passive
56~{ADC0_SE13}/TSI0_CH8/PTB3/LPI2C0_SDA/TPM2_CH1/LPSPI1_PCS3/~{LPUART0_CTS_b}/FXIO0_D11passive
57PTB7/LPSPI1_PCS1passive
58PTB8/LPSPI1_PCS0/FXIO0_D12passive
59PTB9/LPSPI1_SCK/FXIO0_D13passive
60PTB10/LPSPI1_PCS0/FXIO0_D14passive
61PTB11/LPSPI1_SCK/TPM2_CLKIN/FXIO0_D15passive
62TSI0_CH9/PTB16/LPSPI1_SOUT/LPUART0_RX/TPM0_CLKIN/LPSPI2_PCS3/FXIO0_D16passive
63TSI0_CH10/PTB17/LPSPI1_SIN/LPUART0_TX/TPM1_CLKIN/LPSPI2_PCS2/FXIO0_D17passive
64TSI0_CH11/PTB18/TPM2_CH0/LPI2C1_HREQ/FXIO0_D18passive
65TSI0_CH12/PTB19/TPM2_CH1/LPSPI2_PCS1/FXIO0_D19passive
66PTB20/LPSPI2_PCS0/CMP0_OUTpassive
67PTB21/LPSPI2_SCK/CMP1_OUTpassive
68PTB22/LPSPI2_SOUTpassive
69PTB23/LPSPI2_SINpassive
70ADC0_SE14/TSI0_CH13/PTC0/LPSPI2_PCS1/USB_SOF_OUT/CMP0_OUTpassive
71~{ADC0_SE15}/TSI0_CH14/PTC1/LLWU_P6/LPI2C1_SCL/~{LPUART1_RTS_b}/TPM0_CH0passive
72~{ADC0_SE11}/CMP1_IN0/TSI0_CH15/PTC2/LPI2C1_SDA/~{LPUART1_CTS_b}/TPM0_CH1passive
73CMP1_IN1/PTC3/LLWU_P7/LPSPI0_PCS1/LPUART1_RX/TPM0_CH2/CLKOUTpassive
74VSS74passive
75VDD75passive
76PTC4/LLWU_P8/LPSPI0_PCS0/LPUART1_TX/TPM0_CH3/CMP1_OUTpassive
77PTC5/LLWU_P9/LPSPI0_SCK/LPTMR0_ALT2/LPTMR1_ALT2/CMP0_OUTpassive
78CMP0_IN0/PTC6/LLWU_P10/LPSPI0_SOUTpassive
79CMP0_IN1/PTC7/LPSPI0_SIN/USB_SOF_OUT/FXIO0_D20passive
80CMP0_IN2/PTC8/LPI2C0_SCL/TPM0_CH4/FXIO0_D21passive
81CMP0_IN3/PTC9/LPI2C0_SDA/TPM0_CH5/FXIO0_D22passive
82PTC10/LPI2C1_SCL/FXIO0_D23passive
83PTC11/LLWU_P11/LPI2C1_SDApassive
84PTC12/LPI2C1_SCLS/TPM0_CLKINpassive
85PTC13/LPI2C1_SDAS/TPM1_CLKINpassive
86PTC14/EMVSIM0_CLKpassive
87PTC15/EMVSIM0_RSTpassive
88VSS88passive
89VDD89passive
90PTC16/EMVSIM0_VCCENpassive
91PTC17/EMVSIM0_IO/LPSPI0_PCS3passive
92PTC18/EMVSIM0_PD/LPSPI0_PCS2passive
93~{PTD0}/LLWU_P12/LPSPI0_PCS0/~{LPUART2_RTS_b}/TPM0_CH0/FXIO0_D0passive
94~{ADC0_SE5b}/PTD1/LPSPI0_SCK/~{LPUART2_CTS_b}/TPM0_CH1/FXIO0_D1passive
95PTD2/LLWU_P13/LPSPI0_SOUT/LPUART2_RX/TPM0_CH2/FXIO0_D2passive
96PTD3/LPSPI0_SIN/LPUART2_TX/TPM0_CH3/FXIO0_D3passive
97~{PTD4}/LLWU_P14/LPSPI1_PCS0/LPUART2_RX/TPM0_CH4/~{LPUART0_RTS_b}/FXIO0_D4passive
98~{ADC0_SE6b}/PTD5/LPSPI1_SCK/LPUART2_TX/TPM0_CH5/~{LPUART0_CTS_b}/FXIO0_D5passive
99ADC0_SE7b/PTD6/LLWU_P15/LPSPI1_SOUT/LPUART0_RX/FXIO0_D6passive
100PTD7/LPSPI1_SIN/LPUART0_TX/FXIO0_D7passive

Provenance

Credit
Celestial Altium Library by Issus and contributors (https://github.com/issus/altium-library)
Licence
LicenseRef-Celestial-Altium
Link method
none
Cross-check
not confirmed