MICROCHIP AVR128DB64 QFN64
celestial-altium-MCU_ATMEGA
Symbol
64 pins- Units
- 2
- Kind
- part
- Grid
- on 1.27 mm
Footprint
noneno footprint linked
This symbol carries no usable footprint reference, so nothing is linked. Generating one is a better answer than guessing.
3D model
noneno 3D model
The footprint references no model, or the referenced model is not in the upstream package set.
Pins and pads
No footprint is linked, so there is nothing to cross-check.
| Pin | Name | Type |
|---|---|---|
| 1 | PA3/CCL_LUT0_OUT0/TCA0_WO3/TCB1_WO0/TWI0_SCL/USART0_XDIR | passive |
| 2 | PA4/SPI0_MOSI/TCA0_WO4/TCD0_WOA/USART0_TXD | passive |
| 3 | PA5/SPI0_MISO/TCA0_WO5/TCD0_WOB1/USART0_RXD | passive |
| 4 | PA6/CCL_LUT0_OUT0/SPI0_SCK/TCD0_WOC2/USART0_XCK | passive |
| 5 | PA7/AC0/AC1/AC2/CLKCTRL/EVSYS/SPI0/TCD0/USART0/ZCD0/ZCD1/ZCD2 | passive |
| 6 | VDD0 | passive |
| 7 | GND0 | passive |
| 8 | PB0/CCL_LUT4_IN0/TCA0_WO0/TCA1_WO0/USART3_TXD | passive |
| 9 | PB1/CCL_LUT4_IN1/TCA0_WO1/TCA1_WO1/USART3_RXD | passive |
| 10 | PB2/CCL_LUT4_IN2/EVSYS_EVOUT1/TCA0_WO2/TCA1_WO2/TWI1_SDA/USART3_XCK | passive |
| 11 | PB3/CCL_LUT4_OUT0/TCA0_WO3/TCA1_WO3/TWI1_SCL/USART3_XDIR | passive |
| 12 | PB4/SPI1_MOSI/TCA0_WO4/TCA1_WO4/TCB2_WO0/TCD0_WOA/USART3_TXD | passive |
| 13 | PB5/SPI1_MISO/TCA0_WO5/TCA1_WO5/TCB3_WO0/TCD0_WOB1/USART3_RXD | passive |
| 14 | PB6/CCL_LUT4_OUT0/SPI1_SCK/TCD0_WOC2/TWI1_SDA/USART3_XCK | passive |
| 15 | PB7/EVSYS_EVOUT1/SPI1_SS/TCD0_WOD3/TWI1_SCL/USART3_XDIR | passive |
| 16 | PC0/CCL_LUT1_IN0/SPI1_MOSI/TCA0_WO0/TCB2_WO0/USART1_TXD | passive |
| 17 | PC1/CCL_LUT1_IN1/SPI1_MISO/TCA0_WO1/TCB3_WO0/USART1_RXD | passive |
| 18 | PC2/CCL_LUT1_IN2/EVSYS_EVOUT2/SPI1_SCK/TCA0_WO2/TWI0_SDA/USART1_XCK | passive |
| 19 | PC3/CCL_LUT1_OUT0/SPI1_SS/TCA0_WO3/TWI0_SCL/USART1_XDIR | passive |
| 20 | VDDIO2 | passive |
| 21 | GND1 | passive |
| 22 | PC4/SPI1_MOSI/TCA0_WO4/TCA1_WO0/USART1_TXD | passive |
| 23 | PC5/SPI1_MISO/TCA0_WO5/TCA1_WO1/USART1_RXD | passive |
| 24 | PC6/AC0_OUT0/AC1_OUT0/AC2_OUT0/CCL_LUT1_OUT0/SPI1_SCK/TCA1_WO2/TCB4_WO0/TWI0_SDA/USART1_XCK | passive |
| 25 | PC7/EVSYS_EVOUT2/SPI1_SS/TWI0_SCL/USART1_XDIR/ZCD0_OUT/ZCD1_OUT/ZCD2_OUT | passive |
| 26 | PD0/~{AC0_N1}/~{AC1_N1}/~{AC2_N1}/ADC0_AIN0/CCL_LUT2_IN0/TCA0_WO0 | passive |
| 27 | PD1/ADC0_AIN1/CCL_LUT2_IN1/OPAMP_OP0INP/TCA0_WO1/ZCD0_IN | passive |
| 28 | PD2/AC0_P0/AC1_P0/AC2_P0/ADC0_AIN2/CCL_LUT2_IN2/EVSYS_EVOUT3/OPAMP_OP0OUT/TCA0_WO2 | passive |
| 29 | PD3/~{AC0_N0}/AC1_P1/ADC0_AIN3/CCL_LUT2_OUT0/OPAMP_OP0INN/TCA0_WO3 | passive |
| 30 | PD4/AC1_P2/AC2_P1/ADC0_AIN4/OPAMP_OP1INP/TCA0_WO4 | passive |
| 31 | PD5/~{AC1_N0}/ADC0_AIN5/OPAMP_OP1OUT/TCA0_WO5 | passive |
| 32 | PD6/AC0_P3/AC1_P3/AC2_P3/ADC0_AIN6/CCL_LUT2_OUT0/DAC0_OUT0 | passive |
| 33 | PD7/~{AC0_N2}/~{AC1_N2}/~{AC2_N0}/~{AC2_N2}/ADC0_AIN7/EVSYS_EVOUT3/OPAMP_OP1INN | passive |
| 34 | AVDD | passive |
| 35 | AGND | passive |
| 36 | PE0/AC0_P1/ADC0_AIN8/SPI0_MOSI/TCA0_WO0/USART4_TXD | passive |
| 37 | PE1/AC2_P2/ADC0_AIN9/OPAMP_OP2INP/SPI0_MISO/TCA0_WO1/USART4_RXD | passive |
| 38 | PE2/AC0_P2/ADC0_AIN10/EVSYS_EVOUT4/OPAMP_OP2OUT/SPI0_SCK/TCA0_WO2/USART4_XCK | passive |
| 39 | PE3/ADC0_AIN11/OPAMP_OP2INN/SPI0_SS/TCA0_WO3/USART4_XDIR/ZCD1_IN | passive |
| 40 | PE4/ADC0_AIN12/TCA0_WO4/TCA1_WO0/USART4_TXD | passive |
| 41 | PE5/ADC0_AIN13/TCA0_WO5/TCA1_WO1/USART4_RXD | passive |
| 42 | PE6/ADC0_AIN14/TCA1_WO2/USART4_XCK | passive |
| 43 | PE7/ADC0_AIN15/EVSYS_EVOUT4/USART4_XDIR/ZCD2_IN | passive |
| 44 | PF0/ADC0_AIN16/CCL_LUT3_IN0/CLKCTRL_XTAL32K1/TCA0_WO0/TCD0_WOA/USART2_TXD | passive |
| 45 | PF1/ADC0_AIN17/CCL_LUT3_IN1/CLKCTRL_XTAL32K2/TCA0_WO1/TCD0_WOB1/USART2_RXD | passive |
| 46 | PF2/ADC0_AIN18/CCL_LUT3_IN2/EVSYS_EVOUT5/TCA0_WO2/TCD0_WOC2/TWI1_SDA/USART2_XCK | passive |
| 47 | PF3/ADC0_AIN19/CCL_LUT3_OUT0/TCA0_WO3/TCD0_WOD3/TWI1_SCL/USART2_XDIR | passive |
| 48 | PF4/ADC0_AIN20/TCA0_WO4/TCB0_WO0/USART2_TXD | passive |
| 49 | PF5/ADC0_AIN21/TCA0_WO5/TCB1_WO0/USART2_RXD | passive |
| 50 | PF6/RSTCTRL_RESET | passive |
| 51 | UPDI | passive |
| 52 | PG0/CCL_LUT5_IN0/TCA0_WO0/TCA1_WO0/USART5_TXD | passive |
| 53 | PG1/CCL_LUT5_IN1/TCA0_WO1/TCA1_WO1/USART5_RXD | passive |
| 54 | PG2/CCL_LUT5_IN2/EVSYS_EVOUT6/TCA0_WO2/TCA1_WO2/USART5_XCK | passive |
| 55 | PG3/CCL_LUT5_OUT0/TCA0_WO3/TCA1_WO3/TCB4_WO0/USART5_XDIR | passive |
| 56 | VDD2 | passive |
| 57 | GND2 | passive |
| 58 | PG4/SPI0_MOSI/TCA0_WO4/TCA1_WO4/TCD0_WOA/USART5_TXD | passive |
| 59 | PG5/SPI0_MISO/TCA0_WO5/TCA1_WO5/TCD0_WOB1/USART5_RXD | passive |
| 60 | PG6/CCL_LUT5_OUT0/SPI0_SCK/TCD0_WOC2/USART5_XCK | passive |
| 61 | PG7/EVSYS_EVOUT6/SPI0_SS/TCD0_WOD3/USART5_XDIR | passive |
| 62 | PA0/CCL_LUT0_IN0/CLKCTRL_EXTCLK/CLKCTRL_XTALHF1/TCA0_WO0/USART0_TXD | passive |
| 63 | PA1/CCL_LUT0_IN1/CLKCTRL_XTALHF2/TCA0_WO1/USART0_RXD | passive |
| 64 | PA2/CCL_LUT0_IN2/EVSYS_EVOUT0/TCA0_WO2/TCB0_WO0/TWI0_SDA/USART0_XCK | passive |
Provenance
- Source
- celestial-altium-symbols
- Credit
- Celestial Altium Library by Issus and contributors (https://github.com/issus/altium-library)
- Licence
- LicenseRef-Celestial-Altium
- Link method
- none
- Cross-check
- not confirmed
