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NXP MCXA153VFT QFN48

celestial-altium-MCU_NXP

Symbol

49 pins
Schematic symbol for NXP MCXA153VFT QFN48
Units
2
Kind
part
Grid
on 1.27 mm

Footprint

none
no footprint linked

This symbol carries no usable footprint reference, so nothing is linked. Generating one is a better answer than guessing.

3D model

none
no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

No footprint is linked, so there is nothing to cross-check.

PinNameType
1P1_8/WUU0_IN10/LPUART1_RXD/LPI2C0_SDA/CT_INP8/CT0_MAT2/I3C0_SDApassive
2P1_9/LPUART1_TXD/LPI2C0_SCL/CT_INP9/CT0_MAT3/I3C0_SCLpassive
3~{P1_10}/~{LPUART1_RTS_B}/LPI2C0_SDAS/CT2_MAT0/ADC0_A8passive
4~{P1_11}/WUU0_IN11/TRIG_OUT2/~{LPUART1_CTS_B}/LPI2C0_SCLS/CT2_MAT1/I3C0_PUR/ADC0_A9passive
5~{P1_29}/~{RESET_B}/SPC_LPREQpassive
6P1_30/TRIG_OUT3/LPI2C0_SDA/CT_INP16/I3C0_SDA/XTAL48Mpassive
7P1_31/TRIG_IN4/LPI2C0_SCL/CT_INP17/I3C0_SCL/EXTAL48Mpassive
8VDD_ANA/VREFHpassive
9VDDpassive
10P2_0/WUU0_IN18/TRIG_IN6/LPUART0_RXD/CT_INP16/CT2_MAT0/ADC0_A0passive
11P2_1/TRIG_IN7/LPUART0_TXD/CT_INP17/CT2_MAT1/ADC0_A1passive
12~{P2_2}/TRIG_IN6/~{LPUART0_RTS_B}/LPUART2_TXD/CT_INP12/CT2_MAT2/ADC0_A4/CMP0_IN0passive
13~{P2_3}/WUU0_IN19/TRIG_IN7/~{LPUART0_CTS_B}/LPUART2_RXD/CT_INP13/CT2_MAT3/ADC0_A2/CMP1_IN0passive
14P2_6/TRIG_OUT4/LPSPI1_PCS1/CT_INP18/CT1_MAT2/ADC0_A3passive
15P2_7/TRIG_IN5/CT_INP19/CT1_MAT3/VREFI/ADC0_A7passive
16P2_12/WUU0_IN20/USB0_VBUS_DET/LPSPI1_SCK/LPUART1_RXD/CT0_MAT0/ADC0_A5passive
17P2_13/TRIG_IN8/LPSPI1_SDO/LPUART1_TXD/CT0_MAT1passive
18~{P2_16}/LPSPI1_SDI/~{LPUART1_RTS_B}/CT0_MAT2/ADC0_A6passive
19VDD_USBpassive
20USB0_DM/WUU0_IN28passive
21USB0_DP/WUU0_IN29passive
22VDDpassive
23P3_31/LPTMR0_ALT2/TRIG_IN10/CT0_MAT3/ADC0_A12passive
24P3_30/TRIG_OUT6/CT0_MAT2/ADC0_A13passive
25~{P3_29}/WUU0_IN27/~{ISPMODE_N}/CT_INP3/ADC0_A14passive
26P3_28/WUU0_IN26/TRIG_IN11/LPI2C0_SDA/CT_INP12passive
27P3_27/TRIG_OUT7/LPI2C0_SCL/CT_INP13passive
28P3_14/WUU0_IN25/LPUART2_RXD/CT_INP6/PWM0_X2passive
29~{P3_13}/~{LPUART2_CTS_B}/CT1_MAT3/PWM0_X1passive
30~{P3_12}/~{LPUART2_RTS_B}/CT1_MAT2/PWM0_X0passive
31~{P3_11}/WUU0_IN24/TRIG_IN6/LPSPI1_PCS0/~{LPUART1_CTS_B}/CT1_MAT1/~{PWM0_B2}passive
32~{P3_10}/TRIG_IN5/LPSPI1_SCK/~{LPUART1_RTS_B}/CT1_MAT0/PWM0_A2passive
33~{P3_9}/TRIG_IN4/LPSPI1_SDI/LPUART1_TXD/CT_INP5/~{PWM0_B1}passive
34P3_8/WUU0_IN23/TRIG_IN3/LPSPI1_SDO/LPUART1_RXD/CT_INP4/PWM0_A1/CLKOUTpassive
35~{P3_1}/TRIG_IN1/CT_INP17/~{PWM0_B0}/FREQME_CLK_OUT0passive
36P3_0/WUU0_IN22/TRIG_IN0/CT_INP16/PWM0_A0passive
37VDDpassive
38~{P0_0}/TMS/SWDIO/~{LPUART0_RTS_B}/LPSPI0_PCS0/CT_INP0passive
39~{P0_1}/TCLK/SWCLK/~{LPUART0_CTS_B}/LPSPI0_SDI/CT_INP1passive
40P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/I3C0_PURpassive
41P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/CMP0_OUT/CMP1_IN1passive
42P0_6/LPI2C0_HREQ/LPSPI0_PCS1/CT_INP2/CMP1_OUT/CLKOUT/ADC0_A15passive
43P0_16/WUU0_IN2/LPI2C0_SDA/LPSPI0_PCS2/CT0_MAT0/UTICK_CAP2/I3C0_SDApassive
44P0_17/LPI2C0_SCL/LPSPI0_PCS3/CT0_MAT1/UTICK_CAP3/I3C0_SCLpassive
45P1_0/WUU0_IN6/LPTMR0_ALT3/TRIG_IN0/LPSPI0_SDO/LPI2C0_SDA/CT_INP4/CT0_MAT2/ADC0_A16/CMP0_IN3passive
46P1_1/TRIG_IN1/LPSPI0_SCK/LPI2C0_SCL/CT_INP5/CT0_MAT3/ADC0_A17/CMP1_IN3passive
47P1_2/TRIG_OUT0/LPSPI0_SDI/LPI2C0_SDAS/CT1_MAT0/CT_INP0/ADC0_A18passive
48P1_3/WUU0_IN7/TRIG_OUT1/LPSPI0_PCS0/LPI2C0_SCLS/CT1_MAT1/CT_INP1/ADC0_A19/CMP0_IN1passive
49VSSpassive

Provenance

Credit
Celestial Altium Library by Issus and contributors (https://github.com/issus/altium-library)
Licence
LicenseRef-Celestial-Altium
Link method
none
Cross-check
not confirmed