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ST MICROELECTRONICS STM32F413V(

celestial-altium-MCU_STM32

Symbol

100 pins
Schematic symbol for ST MICROELECTRONICS STM32F413V(
Units
5
Kind
part
Grid
on 1.27 mm

Footprint

none
no footprint linked

This symbol carries no usable footprint reference, so nothing is linked. Generating one is a better answer than guessing.

3D model

none
no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

No footprint is linked, so there is nothing to cross-check.

PinNameType
A1PE3/FSMC_A19/~{SAI1_SD_B}/SYS_TRACED0/UART10_TXpassive
A2PE1/DFSDM2_DATIN4/~{FSMC_NBL1}/UART8_TXpassive
A3PB8/CAN1/DFSDM2/I2C1/I2C3/I2S5/LPTIM1/SDIO/SPI5/TIM10/TIM4/UART5passive
A4BOOT0passive
A5PD7/DFSDM1_CKIN1/~{FSMC_NE1}/USART2_CKpassive
A6PD5/DFSDM2_CKOUT/~{FSMC_NWE}/USART2_TXpassive
A7PB4/CAN3_TX/I2C3_SDA/I2S3_ext_SD/SAI1_SCK_A/SDIO_D0/SPI1_MISO/SPI3_MISO/SYS_JTRST/TIM3_CH1/UART7_TXpassive
A8PB3/CAN3/FMPI2C1/I2C2/I2S1/I2S3/SAI1/SPI1/SPI3/SYS/TIM2/UART7/USART1passive
A9PA15/ADC1/CAN3/I2S1/I2S3/SAI1/SPI1/SPI3/SYS/TIM2/UART7/USART1passive
B1PE4/DFSDM1_DATIN3/FSMC_A20/I2S4_WS/I2S5_WS/SAI1_SD_A/~{SPI4_NSS}/~{SPI5_NSS}/SYS_TRACED1passive
B2PE2/FSMC_A23/I2S4_CK/I2S5_CK/~{QUADSPI_BK1_IO2}/SAI1_MCLK_A/SPI4_SCK/SPI5_SCK/SYS_TRACECLK/UART10_RXpassive
B3PB9/CAN1/DAC/DFSDM2/I2C1/I2C2/I2S2/SDIO/SPI2/TIM11/TIM4/UART5passive
B4PB7/DFSDM2_DATIN7/~{FSMC_NL}/I2C1_SDA/LPTIM1_IN2/TIM4_CH2/USART1_RXpassive
B5PB6/CAN2_TX/DFSDM2_CKIN7/I2C1_SCL/LPTIM1_ETR/~{QUADSPI_BK1_NCS}/SDIO_D0/TIM4_CH1/UART5_TX/USART1_TXpassive
B6PD6/DFSDM1_DATIN1/~{FSMC_NWAIT}/I2S3_SD/SPI3_MOSI/USART2_RXpassive
B7PD4/DFSDM1_CKIN0/~{FSMC_NOE}/USART2_RTSpassive
B8PD3/DFSDM1_DATIN0/FSMC_CLK/I2S2_CK/QUADSPI_CLK/SPI2_SCK/SYS_TRACED1/USART2_CTSpassive
B9PD1/CAN1_TX/DFSDM2_DATIN6/FSMC_D3/FSMC_DA3/UART4_TXpassive
C1PC13/RTC_AF1passive
C2PE5/DFSDM1_CKIN3/FSMC_A21/SAI1_SCK_A/SPI4_MISO/SPI5_MISO/SYS_TRACED2/TIM9_CH1passive
C3PE0/DFSDM2_CKIN4/~{FSMC_NBL0}/TIM4_ETR/UART8_RXpassive
C4VDDpassive
C5PB5/CAN2/I2C1/I2S1/I2S3/LPTIM1/SAI1/SDIO/SPI1/SPI3/TIM3/UART5passive
C8PD2/DFSDM2_CKOUT/~{FSMC_NWE}/SDIO_CMD/TIM3_ETR/UART5_RXpassive
C9PD0/CAN1_RX/DFSDM2_CKIN6/FSMC_D2/FSMC_DA2/UART4_RXpassive
D1PC14-OSC32_IN/RCC_OSC32_INpassive
D2PE6/FSMC_A22/I2S4_SD/I2S5_SD/SAI1_FS_A/SPI4_MOSI/SPI5_MOSI/SYS_TRACED3/TIM9_CH2passive
D3VSSpassive
E1PC15-OSC32_OUT/ADC1_EXTI15/RCC_OSC32_OUTpassive
E2VBATpassive
E3BYPASS_REGpassive
F1PH0_-_OSC_IN/RCC_OSC_INpassive
F2VSSpassive
G1PH1_-_OSC_OUT/RCC_OSC_OUTpassive
G2VDDpassive
H1PC0/ADC1_IN10/DFSDM2_CKIN4/LPTIM1_IN1/~{SAI1_MCLK_B}/SYS_WKUP2passive
H2NRSTpassive
H3PDR_ONpassive
J1VSSApassive
J2PC1/ADC1_IN11/DFSDM2_DATIN4/LPTIM1_OUT/~{SAI1_SD_B}/SYS_WKUP3passive
J3PC2/ADC1_IN12/DFSDM1_CKOUT/DFSDM2_DATIN7/~{FSMC_NWE}/I2S2_ext_SD/LPTIM1_IN2/~{SAI1_SCK_B}/SPI2_MISOpassive
K1VREF-passive
K2PC3/ADC1_IN13/DFSDM2_CKIN7/FSMC_A0/I2S2_SD/LPTIM1_ETR/~{SAI1_FS_B}/SPI2_MOSIpassive
K3PA2/ADC1_IN2/FSMC_D4/FSMC_DA4/I2S_CKIN/TIM2_CH3/TIM5_CH3/TIM9_CH1/USART2_TXpassive
K4PA5/ADC1_IN5/DAC_OUT2/DFSDM1_CKIN1/FSMC_D7/FSMC_DA7/I2S1_CK/SPI1_SCK/TIM2_CH1/TIM2_ETR/TIM8_CH1Npassive
K5PC4/ADC1_IN14/DFSDM2_CKIN2/~{FSMC_NE4}/I2S1_MCK/~{QUADSPI_BK2_IO2}passive
K8PD9/DAC_EXTI9/FSMC_D14/FSMC_DA14/USART3_RXpassive
K9PB11/ADC1_EXTI11/I2C2_SDA/I2S_CKIN/TIM2_CH4/USART3_RXpassive
L1VREF+passive
L2PA0/ADC1_IN0/SYS_WKUP1/TIM2_CH1/TIM2_ETR/TIM5_CH1/TIM8_ETR/UART4_TX/USART2_CTSpassive
L3PA3/ADC1_IN3/FSMC_D5/FSMC_DA5/I2S2_MCK/~{SAI1_SD_B}/TIM2_CH4/TIM5_CH4/TIM9_CH2/USART2_RXpassive
L4PA6/ADC1/DFSDM2/I2S2/QUADSPI/SDIO/SPI1/TIM13/TIM1/TIM3/TIM8passive
L5PC5/ADC1_IN15/DFSDM2_DATIN2/FMPI2C1_SMBA/~{FSMC_NOE}/~{QUADSPI_BK2_IO3}/USART3_RXpassive
L6PB2/DFSDM1_CKIN0/LPTIM1_OUT/QUADSPI_CLKpassive
L7PE8/DFSDM1_CKIN2/FSMC_D5/FSMC_DA5/~{QUADSPI_BK2_IO1}/TIM1_CH1N/UART7_TXpassive
L8PE10/DFSDM2_DATIN0/FSMC_D7/FSMC_DA7/~{QUADSPI_BK2_IO3}/TIM1_CH2Npassive
L9PE12/DFSDM2_DATIN7/FSMC_D9/FSMC_DA9/I2S4_CK/I2S5_CK/SPI4_SCK/SPI5_SCK/TIM1_CH3Npassive
M1VDDApassive
M2PA1/ADC1_IN1/I2S4_SD/~{QUADSPI_BK1_IO3}/SPI4_MOSI/TIM2_CH2/TIM5_CH2/UART4_RX/USART2_RTSpassive
M3PA4/ADC1_IN4/DAC_OUT1/DFSDM1_DATIN1/FSMC_D6/FSMC_DA6/I2S1_WS/I2S3_WS/~{SPI1_NSS}/~{SPI3_NSS}/USART2_CKpassive
M4PA7/ADC1_IN7/DFSDM2_DATIN1/I2S1_SD/~{QUADSPI_BK2_IO1}/SPI1_MOSI/TIM14_CH1/TIM1_CH1N/TIM3_CH2/TIM8_CH1Npassive
M5PB0/ADC1_IN8/I2S5_CK/SPI5_SCK/TIM1_CH2N/TIM3_CH3/TIM8_CH2Npassive
M6PB1/ADC1_IN9/DFSDM1_DATIN0/I2S5_WS/QUADSPI_CLK/~{SPI5_NSS}/TIM1_CH3N/TIM3_CH4/TIM8_CH3Npassive
M7PE7/DFSDM1_DATIN2/FSMC_D4/FSMC_DA4/~{QUADSPI_BK2_IO0}/TIM1_ETR/UART7_RXpassive
M8PE9/DAC_EXTI9/DFSDM1_CKOUT/FSMC_D6/FSMC_DA6/~{QUADSPI_BK2_IO2}/TIM1_CH1passive
M9PE11/ADC1_EXTI11/DFSDM2_CKIN0/FSMC_D8/FSMC_DA8/I2S4_WS/I2S5_WS/~{SPI4_NSS}/~{SPI5_NSS}/TIM1_CH2passive
A10PA14/SYS_JTCK-SWCLKpassive
A11PA13/SYS_JTMS-SWDIOpassive
A12PA12/CAN1_TX/DFSDM2_DATIN5/SPI2_MISO/SPI5_MISO/TIM1_ETR/UART4_TX/USART1_RTS/USART6_RX/USB_OTG_FS_DPpassive
B10PC12/FSMC_D3/FSMC_DA3/I2S3_SD/SDIO_CK/SPI3_MOSI/UART5_TX/USART3_CKpassive
B11PC10/DFSDM2_CKIN5/I2S3_CK/~{QUADSPI_BK1_IO1}/SDIO_D2/SPI3_SCK/USART3_TXpassive
B12PA11/ADC1/CAN1/DFSDM2/I2S2/SPI2/SPI4/TIM1/UART4/USART1/USART6/USBpassive
C10PC11/ADC1/DFSDM2/FSMC/I2S3/QUADSPI/SDIO/SPI3/UART4/USART3passive
C11VCAP_2passive
C12PA10/DFSDM2_DATIN3/I2S2_SD/I2S5_SD/SPI2_MOSI/SPI5_MOSI/TIM1_CH3/USART1_RX/USB_OTG_FS_IDpassive
D10PA9/DAC_EXTI9/DFSDM2_CKIN3/I2C3_SMBA/I2S2_CK/SDIO_D2/SPI2_SCK/TIM1_CH2/USART1_TX/USB_OTG_FS_VBUSpassive
D11PA8/CAN3_RX/DFSDM1_CKOUT/I2C3_SCL/RCC_MCO_1/SDIO_D1/TIM1_CH1/UART7_RX/USART1_CK/USB_OTG_FS_SOFpassive
D12PC9/DAC_EXTI9/DFSDM2_DATIN3/I2C3_SDA/I2S_CKIN/~{QUADSPI_BK1_IO0}/RCC_MCO_2/SDIO_D1/TIM3_CH4/TIM8_CH4passive
E10PC8/DFSDM2_CKIN3/~{QUADSPI_BK1_IO2}/SDIO_D0/TIM3_CH3/TIM8_CH3/USART6_CKpassive
E11PC7/DFSDM1/DFSDM2/FMPI2C1/I2S2/I2S3/SDIO/SPI2/TIM3/TIM8/USART6passive
E12PC6/DFSDM1/DFSDM2/FMPI2C1/FSMC/I2S2/SDIO/TIM3/TIM8/USART6passive
F11VSSpassive
F12VSSpassive
G11VDDpassive
G12VDDpassive
H10PD15/ADC1_EXTI15/DFSDM2_DATIN0/FMPI2C1_SDA/FSMC_D1/FSMC_DA1/TIM4_CH4/UART9_TXpassive
H11PD14/DFSDM2_CKIN0/FMPI2C1_SCL/FSMC_D0/FSMC_DA0/TIM4_CH3/UART9_RXpassive
H12PD13/FMPI2C1_SDA/FSMC_A18/~{QUADSPI_BK1_IO3}/TIM4_CH2passive
J10PD12/DFSDM2_CKIN2/FMPI2C1_SCL/FSMC_A17/~{QUADSPI_BK1_IO1}/TIM4_CH1/USART3_RTSpassive
J11PD11/ADC1_EXTI11/DFSDM2_DATIN2/FMPI2C1_SMBA/FSMC_A16/~{QUADSPI_BK1_IO0}/USART3_CTSpassive
J12PD10/FSMC_D15/FSMC_DA15/UART4_TX/USART3_CKpassive
K10PB15/ADC1/DFSDM1/FMPI2C1/I2S2/RTC/SDIO/SPI2/TIM12/TIM1/TIM8passive
K11PB14/DFSDM1/FMPI2C1/FSMC/I2S2/SDIO/SPI2/TIM12/TIM1/TIM8/USART3passive
K12PB13/CAN2/DFSDM1/FMPI2C1/I2S2/I2S4/SPI2/SPI4/TIM1/UART5/USART3passive
L10PB10/DFSDM2_CKOUT/FMPI2C1_SCL/I2C2_SCL/I2S2_CK/I2S3_MCK/SDIO_D7/SPI2_SCK/TIM2_CH3/USART3_TXpassive
L11VCAP_1passive
L12PB12/CAN2/DFSDM1/FSMC/I2C2/I2S2/I2S3/I2S4/SPI2/SPI3/SPI4/TIM1/UART5/USART3passive
M10PE13/DFSDM2_CKIN7/FSMC_D10/FSMC_DA10/SPI4_MISO/SPI5_MISO/TIM1_CH3passive
M11PE14/DFSDM2_DATIN1/FSMC_D11/FSMC_DA11/I2S4_SD/I2S5_SD/SPI4_MOSI/SPI5_MOSI/TIM1_CH4passive
M12PE15/ADC1_EXTI15/DFSDM2_CKIN1/FSMC_D12/FSMC_DA12/~{TIM1_BKIN}passive

Provenance

Credit
Celestial Altium Library by Issus and contributors (https://github.com/issus/altium-library)
Licence
LicenseRef-Celestial-Altium
Link method
none
Cross-check
not confirmed