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ST MICROELECTRONICS STM32G0B0RE

celestial-altium-MCU_STM32

Symbol

64 pins
Schematic symbol for ST MICROELECTRONICS STM32G0B0RE
Units
3
Kind
part
Grid
on 1.27 mm

Footprint

none
no footprint linked

This symbol carries no usable footprint reference, so nothing is linked. Generating one is a better answer than guessing.

3D model

none
no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

No footprint is linked, so there is nothing to cross-check.

PinNameType
1PC11/ADC1_EXTI11/SPI3_MISO/TIM1_CH4/USART3_RX/USART4_RXpassive
2PC12/SPI3_MOSI/TIM14_CH1/USART5_TXpassive
3PC13/RTC_OUT1/RTC_TAMP_IN1/RTC_TS/SYS_WKUP2/~{TIM1_BK}passive
4PC14-OSC32_IN_(PC14)/RCC_OSC32_IN/~{TIM1_BK2}passive
5PC15-OSC32_OUT_(PC15)/RCC_OSC32_EN/RCC_OSC32_OUT/RCC_OSC_EN/~{TIM15_BK}passive
6VBATpassive
7VREF+passive
8VDDpassive
9VSSpassive
10PF0-OSC_IN_(PF0)/CRS1_SYNC/RCC_OSC_IN/TIM14_CH1passive
11PF1-OSC_OUT_(PF1)/RCC_OSC_EN/RCC_OSC_OUT/TIM15_CH1Npassive
12NRSTpassive
13PC0/I2C3_SCL/USART6_TXpassive
14PC1/I2C3_SDA/TIM15_CH1/USART6_RXpassive
15PC2/I2S2_MCK/SPI2_MISO/TIM15_CH2passive
16PC3/I2S2_SD/SPI2_MOSIpassive
17PA0/ADC1_IN0/I2S2_CK/RTC_TAMP_IN2/SPI2_SCK/SYS_WKUP1/USART2_CTS/~{USART2_NSS}/USART4_TXpassive
18PA1/ADC1_IN1/I2C1_SMBA/I2S1_CK/SPI1_SCK/TIM15_CH1N/USART2_CK/USART2_DE/USART2_RTS/USART4_RXpassive
19PA2/ADC1_IN2/I2S1_SD/RCC_LSCO/SPI1_MOSI/SYS_WKUP4/TIM15_CH1/USART2_TXpassive
20PA3/ADC1_IN3/I2S2_MCK/SPI2_MISO/TIM15_CH2/USART2_RXpassive
21PA4/ADC1_IN4/I2S1_WS/I2S2_SD/RTC_OUT2/~{SPI1_NSS}/SPI2_MOSI/~{SPI3_NSS}/TIM14_CH1/USART6_TX/~{USB_NOE}passive
22PA5/ADC1_IN5/I2S1_CK/SPI1_SCK/USART3_TX/USART6_RXpassive
23PA6/ADC1/I2C2/I2C3/I2S1/SPI1/TIM16/TIM1/TIM3/USART3/USART6passive
24PA7/ADC1/I2C2/I2C3/I2S1/SPI1/TIM14/TIM17/TIM1/TIM3/USART6passive
25PC4/ADC1_IN17/USART1_TX/USART3_TXpassive
26PC5/ADC1_IN18/SYS_WKUP5/USART1_RX/USART3_RXpassive
27PB0/ADC1_IN8/I2S1_WS/~{SPI1_NSS}/TIM1_CH2N/TIM3_CH3/USART3_RX/USART5_TXpassive
28PB1/ADC1_IN9/TIM14_CH1/TIM1_CH3N/TIM3_CH4/USART3_CK/USART3_DE/USART3_RTS/USART5_RXpassive
29PB2/ADC1_IN10/I2S2_MCK/RCC_MCO_2/SPI2_MISO/USART3_TXpassive
30PB10/ADC1_IN11/I2C2_SCL/I2S2_CK/SPI2_SCK/USART3_TXpassive
31PB11/ADC1_EXTI11/ADC1_IN15/I2C2_SDA/I2S2_SD/SPI2_MOSI/USART3_RXpassive
32PB12/ADC1_IN16/I2C2_SMBA/I2S2_WS/~{SPI2_NSS}/~{TIM15_BK}/~{TIM1_BK}passive
33PB13/I2C2_SCL/I2S2_CK/SPI2_SCK/TIM15_CH1N/TIM1_CH1N/USART3_CTS/~{USART3_NSS}passive
34PB14/I2C2/I2S2/SPI2/TIM15/TIM1/USART3/USART6passive
35PB15/I2S2_SD/RTC_REFIN/SPI2_MOSI/TIM15_CH1N/TIM15_CH2/TIM1_CH3N/USART6_CTS/~{USART6_NSS}passive
36PA8/CRS1_SYNC/I2C2_SMBA/I2S2_WS/RCC_MCO/~{SPI2_NSS}/TIM1_CH1passive
37PA9/I2C1_SCL/I2C2_SCL/I2S2_MCK/RCC_MCO/SPI2_MISO/~{TIM15_BK}/TIM1_CH2/USART1_TXpassive
38PC6/TIM3_CH1passive
39PC7/TIM3_CH2passive
40PD8/I2S1_CK/SPI1_SCK/USART3_TXpassive
41PD9/I2S1_WS/~{SPI1_NSS}/~{TIM1_BK2}/USART3_RXpassive
42PA10/I2C1_SDA/I2C2_SDA/I2S2_SD/RCC_MCO_2/SPI2_MOSI/~{TIM17_BK}/TIM1_CH3/USART1_RXpassive
43PA9_[PA11]/I2C1_SCL/I2C2_SCL/I2S2_MCK/RCC_MCO/SPI2_MISO/~{TIM15_BK}/TIM1_CH2/USART1_TXpassive
44PA10_[PA12]/I2C1_SDA/I2C2_SDA/I2S2_SD/RCC_MCO_2/SPI2_MOSI/~{TIM17_BK}/TIM1_CH3/USART1_RXpassive
45PA13/IR_OUT/SYS_SWDIO/~{USB_NOE}passive
46PA14-BOOT0/SYS_SWCLK/USART2_TXpassive
47PA15/I2C2/I2S1/RCC/SPI1/SPI3/USART2/USART3/USART4/USBpassive
48PC8/TIM1_CH1/TIM3_CH3passive
49PC9/I2S_CKIN/TIM1_CH2/TIM3_CH4/~{USB_NOE}passive
50PD0/I2S2_WS/~{SPI2_NSS}/TIM16_CH1passive
51PD1/I2S2_CK/SPI2_SCK/TIM17_CH1passive
52PD2/TIM1_CH1N/TIM3_ETR/USART3_CK/USART3_DE/USART3_RTS/USART5_RXpassive
53PD3/I2S2_MCK/SPI2_MISO/TIM1_CH2N/USART2_CTS/~{USART2_NSS}/USART5_TXpassive
54PD4/I2S2_SD/SPI2_MOSI/TIM1_CH3N/USART2_CK/USART2_DE/USART2_RTS/USART5_CK/USART5_DE/USART5_RTSpassive
55PD5/I2S1_MCK/SPI1_MISO/~{TIM1_BK}/USART2_TX/USART5_CTS/~{USART5_NSS}passive
56PD6/I2S1_SD/SPI1_MOSI/USART2_RXpassive
57PB3/I2C2_SCL/I2C3_SCL/I2S1_CK/SPI1_SCK/SPI3_SCK/TIM1_CH2/USART1_CK/USART1_DE/USART1_RTS/USART5_TXpassive
58PB4/I2C2_SDA/I2C3_SDA/I2S1_MCK/SPI1_MISO/SPI3_MISO/~{TIM17_BK}/TIM3_CH1/USART1_CTS/~{USART1_NSS}/USART5_RXpassive
59PB5/I2C1_SMBA/I2S1_SD/SPI1_MOSI/SPI3_MOSI/SYS_WKUP6/~{TIM16_BK}/TIM3_CH2/USART5_CK/USART5_DE/USART5_RTSpassive
60PB6/I2C1_SCL/I2S2_MCK/SPI2_MISO/TIM16_CH1N/TIM1_CH3/TIM4_CH1/USART1_TX/USART5_CTS/~{USART5_NSS}passive
61PB7/I2C1_SDA/I2S2_SD/SPI2_MOSI/TIM17_CH1N/TIM4_CH2/USART1_RX/USART4_CTS/~{USART4_NSS}passive
62PB8/I2C1_SCL/I2S2_CK/SPI2_SCK/~{TIM15_BK}/TIM16_CH1/TIM4_CH3/USART3_TX/USART6_TXpassive
63PB9/I2C1_SDA/I2S2_WS/IR_OUT/~{SPI2_NSS}/TIM17_CH1/TIM4_CH4/USART3_RX/USART6_RXpassive
64PC10/SPI3_SCK/TIM1_CH3/USART3_TX/USART4_TXpassive

Provenance

Credit
Celestial Altium Library by Issus and contributors (https://github.com/issus/altium-library)
Licence
LicenseRef-Celestial-Altium
Link method
none
Cross-check
not confirmed