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ST MICROELECTRONICS STM32L072V(

celestial-altium-MCU_STM32

Symbol

100 pins
Schematic symbol for ST MICROELECTRONICS STM32L072V(
Units
5
Kind
part
Grid
on 1.27 mm

Footprint

none
no footprint linked

This symbol carries no usable footprint reference, so nothing is linked. Generating one is a better answer than guessing.

3D model

none
no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

No footprint is linked, so there is nothing to cross-check.

PinNameType
A1PE3/TIM22_CH1/TIM3_CH1passive
A2PE1passive
A3PB8/I2C1_SCL/TSC_SYNCpassive
A4BOOT0passive
A5PD7/TIM21_CH2/USART2_CKpassive
A6PD5/USART2_TXpassive
A7PB4/COMP2_INP/I2C3_SDA/SPI1_MISO/TIM22_CH1/TIM3_CH1/TSC_G5_IO2/USART1_CTS/USART5_RXpassive
A8PB3/COMP2_INM/SPI1_SCK/TIM2_CH2/TSC_G5_IO1/USART1_DE/USART1_RTS/USART5_TXpassive
A9PA15/~{SPI1_NSS}/TIM2_CH1/TIM2_ETR/USART2_RX/USART4_DE/USART4_RTSpassive
B1PE4/TIM22_CH2/TIM3_CH2passive
B2PE2/TIM3_ETRpassive
B3PB9/DAC_EXTI9/I2C1_SDA/I2S2_WS/~{SPI2_NSS}passive
B4PB7/COMP2_INP/I2C1_SDA/LPTIM1_IN2/SYS_PVD_IN/TSC_G5_IO4/USART1_RX/USART4_CTSpassive
B5PB6/COMP2_INP/I2C1_SCL/LPTIM1_ETR/TSC_G5_IO3/USART1_TXpassive
B6PD6/USART2_RXpassive
B7PD4/I2S2_SD/SPI2_MOSI/USART2_DE/USART2_RTSpassive
B8PD3/I2S2_MCK/SPI2_MISO/USART2_CTSpassive
B9PD1/I2S2_CK/SPI2_SCKpassive
C1PC13/RTC_OUT_ALARM/RTC_OUT_CALIB/RTC_TAMP1/RTC_TS/SYS_WKUP2passive
C2PE5/TIM21_CH1/TIM3_CH3passive
C3PE0passive
C4VDDpassive
C5PB5/COMP2/I2C1/LPTIM1/SPI1/TIM22/TIM3/USART1/USART5passive
C8PD2/LPUART1_DE/LPUART1_RTS/TIM3_ETR/USART5_RXpassive
C9PD0/I2S2_WS/~{SPI2_NSS}/TIM21_CH1passive
D1PC14-OSC32_IN/RCC_OSC32_INpassive
D2PE6/RTC_TAMP3/SYS_WKUP3/TIM21_CH2/TIM3_CH4passive
D3VSSpassive
E1PC15-OSC32_OUT/RCC_OSC32_OUTpassive
E2VDDpassive
E3VSSpassive
F1PH0-OSC_IN/CRS_SYNC/RCC_OSC_INpassive
F2PH9/DAC_EXTI9passive
G1PH1-OSC_OUT/RCC_OSC_OUTpassive
G2PH10passive
H1PC0/ADC_IN10/I2C3_SCL/LPTIM1_IN1/LPUART1_RX/TSC_G7_IO1passive
H2NRSTpassive
H3VDDpassive
J1VSSApassive
J2PC1/ADC_IN11/I2C3_SDA/LPTIM1_OUT/LPUART1_TX/TSC_G7_IO2passive
J3PC2/ADC_IN12/I2S2_MCK/LPTIM1_IN2/SPI2_MISO/TSC_G7_IO3passive
K1VREF-passive
K2PC3/ADC_IN13/I2S2_SD/LPTIM1_ETR/SPI2_MOSI/TSC_G7_IO4passive
K3PA2/ADC_IN2/COMP2_INM/COMP2_OUT/LPUART1_TX/TIM21_CH1/TIM2_CH3/TSC_G1_IO3/USART2_TXpassive
K4PA5/ADC_IN5/COMP1_INM/COMP2_INM/DAC_OUT2/SPI1_SCK/TIM2_CH1/TIM2_ETR/TSC_G2_IO2passive
K5PC4/ADC_IN14/LPUART1_TXpassive
K8PD9/DAC_EXTI9/LPUART1_RXpassive
K9PD8/LPUART1_TXpassive
L1VREF+passive
L2PA0/ADC/COMP1/RTC/SYS/TIM2/TSC/USART2/USART4passive
L3PA3/ADC_IN3/COMP2_INP/LPUART1_RX/TIM21_CH2/TIM2_CH4/TSC_G1_IO4/USART2_RXpassive
L4PA6/ADC_IN6/COMP1_OUT/LPUART1_CTS/SPI1_MISO/TIM22_CH1/TIM3_CH1/TSC_G2_IO3passive
L5PC5/ADC_IN15/LPUART1_RX/TSC_G3_IO1passive
L6PB2/I2C3_SMBA/LPTIM1_OUT/TSC_G3_IO4passive
L7PE8/USART4_TXpassive
L8PE10/TIM2_CH2/USART5_TXpassive
L9PE12/~{SPI1_NSS}/TIM2_CH4passive
M1VDDApassive
M2PA1/ADC_IN1/COMP1_INP/TIM21_ETR/TIM2_CH2/TSC_G1_IO2/USART2_DE/USART2_RTS/USART4_RXpassive
M3PA4/ADC_IN4/COMP1_INM/COMP2_INM/DAC_OUT1/~{SPI1_NSS}/TIM22_ETR/TSC_G2_IO1/USART2_CKpassive
M4PA7/ADC_IN7/COMP2_OUT/SPI1_MOSI/TIM22_CH2/TIM3_CH2/TSC_G2_IO4passive
M5PB0/ADC_IN8/SYS_VREF_OUT_PB0/TIM3_CH3/TSC_G3_IO2passive
M6PB1/ADC_IN9/LPUART1_DE/LPUART1_RTS/SYS_VREF_OUT_PB1/TIM3_CH4/TSC_G3_IO3passive
M7PE7/USART5_CK/USART5_DE/USART5_RTSpassive
M8PE9/DAC_EXTI9/TIM2_CH1/TIM2_ETR/USART4_RXpassive
M9PE11/ADC_EXTI11/TIM2_CH3/USART5_RXpassive
A10PA14/LPUART1_TX/SYS_SWCLK/USART2_TXpassive
A11PA13/LPUART1_RX/SYS_SWDIO/~{USB_NOE}passive
A12PA12/COMP2_OUT/SPI1_MOSI/TSC_G4_IO4/USART1_DE/USART1_RTS/USB_DPpassive
B10PC12/USART4_CK/USART5_TXpassive
B11PC10/LPUART1_TX/USART4_TXpassive
B12PA11/ADC_EXTI11/COMP1_OUT/SPI1_MISO/TSC_G4_IO3/USART1_CTS/USB_DMpassive
C10PC11/ADC_EXTI11/LPUART1_RX/USART4_RXpassive
C11VDDpassive
C12PA10/I2C1_SDA/TSC_G4_IO2/USART1_RXpassive
D10PA9/DAC_EXTI9/I2C1_SCL/I2C3_SMBA/RCC_MCO/TSC_G4_IO1/USART1_TXpassive
D11PA8/CRS_SYNC/I2C3_SCL/RCC_MCO/USART1_CKpassive
D12PC9/DAC_EXTI9/I2C3_SDA/TIM21_ETR/TIM3_CH4/TSC_G8_IO4/~{USB_NOE}passive
E10PC8/TIM22_ETR/TIM3_CH3/TSC_G8_IO3passive
E11PC7/TIM22_CH2/TIM3_CH2/TSC_G8_IO2passive
E12PC6/TIM22_CH1/TIM3_CH1/TSC_G8_IO1passive
F11VSSpassive
F12VSSpassive
G11VDD_USBpassive
G12VDDpassive
H10PD15/CRS_SYNCpassive
H11PD14passive
H12PD13passive
J10PD12/LPUART1_DE/LPUART1_RTSpassive
J11PD11/ADC_EXTI11/LPUART1_CTSpassive
J12PD10passive
K10PB15/I2S2_SD/RTC_REFIN/SPI2_MOSIpassive
K11PB14/I2C2/I2S2/LPUART1/RTC/SPI2/TIM21/TSCpassive
K12PB13/I2C2_SCL/I2S2_CK/LPUART1_CTS/RCC_MCO/SPI2_SCK/TIM21_CH1/TSC_G6_IO3passive
L10PB10/I2C2_SCL/LPUART1_RX/LPUART1_TX/SPI2_SCK/TIM2_CH3/TSC_SYNCpassive
L11PB11/ADC_EXTI11/I2C2_SDA/LPUART1_RX/LPUART1_TX/TIM2_CH4/TSC_G6_IO1passive
L12PB12/I2S2_WS/LPUART1_DE/LPUART1_RTS/~{SPI2_NSS}/TSC_G6_IO2passive
M10PE13/SPI1_SCKpassive
M11PE14/SPI1_MISOpassive
M12PE15/SPI1_MOSIpassive

Provenance

Credit
Celestial Altium Library by Issus and contributors (https://github.com/issus/altium-library)
Licence
LicenseRef-Celestial-Altium
Link method
none
Cross-check
not confirmed