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ST MICROELECTRONICS STM32MP131A

celestial-altium-MCU_STM32

Symbol

289 pins
Schematic symbol for ST MICROELECTRONICS STM32MP131A
Units
10
Kind
part
Grid
on 1.27 mm

Footprint

none
no footprint linked

This symbol carries no usable footprint reference, so nothing is linked. Generating one is a better answer than guessing.

3D model

none
no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

No footprint is linked, so there is nothing to cross-check.

PinNameType
A1VSSpassive
A2PD4/DFSDM1_CKIN0/~{FMC_NOE}/I2S3_SDI/QUADSPI_CLK/SPI3_MISO/USART2_DE/USART2_RTSpassive
A3PE9/FMC_D6/FMC_DA6/HDP_HDP3/~{QUADSPI_BK1_IO1}/TIM1_CH1passive
A4PG0/FMC_A10passive
A5PD15/ADC2_EXTI15/DFSDM1_DATIN2/FMC_D1/FMC_DA1/~{QUADSPI_BK1_IO3}/TIM4_CH4/USART2_RXpassive
A6PE15/ADC2/FMC/HDP/I2C4/TIM1/TIM2/USART2passive
A7PB12/DEBUG_TRACED10/DFSDM1_DATIN1/I2C2_SMBA/SDMMC1_D5/UART5_RX/UART7_DE/UART7_RTS/USART3_RXpassive
A8PF1/DEBUG_TRACED7/FMC_A1/HDP_HDP7/I2C2_SDA/I2S3_SDO/SPI3_MOSIpassive
A9PC7/DEBUG/HDP/I2S2/SDMMC1/SDMMC2/TIM3/TIM8/USART3/USART6passive
B1PE12/FMC_D9/FMC_DA9/HDP_HDP4/I2S4_CK/SPI4_SCK/TIM1_CH3N/UART8_DE/UART8_RTSpassive
B2PD8/I2S4_WS/UART4_RX/USART2_TX/USART3_TXpassive
B3PE0/FMC_A11/UART8_RXpassive
B4PD5/~{FMC_NWE}/~{QUADSPI_BK1_IO0}passive
B5PD9/DEBUG_TRACECLK/DFSDM1_DATIN3/FMC_D14/FMC_DA14/SDMMC2_CDIRpassive
B6PH14/DFSDM1_DATIN2/I2C3_SDA/UART4_RXpassive
B7PF2/DEBUG_TRACED1/DFSDM1_CKIN1/FMC_A2/I2C2_SCL/SDMMC1_D0DIR/SDMMC2_D0DIR/USART6_CKpassive
B8VSSpassive
B9PF3/FMC_A3/I2C5_SDA/I2S3_WS/I2S4_SDI/LPTIM2_IN2/~{SPI3_NSS}/SPI4_MISOpassive
C1PE13/FMC_D10/FMC_DA10/I2C5_SDA/I2S4_SDI/SPI4_MISO/TIM1_CH3passive
C2PD1/FMC_D3/FMC_DA3/I2C5_SCL/I2S4_SDO/~{QUADSPI_BK1_NCS}/SPI4_MOSI/UART4_TXpassive
C3PE1/~{FMC_NBL1}/LPTIM1_IN2/UART8_TXpassive
C4PE7/FMC_D4/FMC_DA4/LPTIM2_IN1/TIM1_ETR/UART5_TXpassive
C5VSSpassive
C6VDDpassive
C7PE10/FMC_D7/FMC_DA7/TIM1_CH2N/UART7_RXpassive
C8PG7/DEBUG_TRACED8/I2S3_SDI/SDMMC2_CKIN/SPI3_MISO/TIM1_ETR/UART7_CTSpassive
C9PG4/DEBUG_TRACED1/DFSDM1_CKIN3/FMC_A14/HDP_HDP1/SDMMC2_D123DIR/~{TIM1_BKIN2}/USART3_RXpassive
D1PF5/DEBUG_TRACED12/DFSDM1_CKIN0/FMC_A5/I2C1_SMBApassive
D2PA9/DFSDM1_DATIN0/~{FMC_NWAIT}/I2C3_SMBA/TIM1_CH2/UART4_TX/USART1_TXpassive
D3PD10/FMC_D15/FMC_DA15/I2C5_SMBA/I2S4_WS/RTC_REFIN/~{SPI4_NSS}/USART3_CKpassive
D4VDDCPUpassive
D5PB7/~{FMC_NCE2}/~{FMC_NL}/I2C4_SDA/I2S4_CK/TIM17_CH1N/TIM4_CH2passive
D6VDDCPUpassive
D7PD12/FMC_A17/FMC_ALE/I2C1_SCL/LPTIM1_IN1/TIM4_CH1/USART3_DE/USART3_RTSpassive
D8VDDCPUpassive
D9PH9/FMC_A20/I2S4_CK/SPI4_SCK/TIM12_CH2/TIM1_CH4passive
E1PD0/FMC_D2/FMC_DA2/SAI1_CK1/SAI1_MCLK_Apassive
E2PE14/FMC_D11/FMC_DA11/~{QUADSPI_BK1_NCS}/~{QUADSPI_BK2_IO2}/SAI1_D4/TAMP_IN6/~{TIM1_BKIN}/UART8_DE/UART8_RTSpassive
E3VSSpassive
E4PE11/ADC2/ETH1/FMC/I2S4/SAI1/SPI4/TIM1/USART2/USART6passive
E5VDDCPUpassive
E6VSSpassive
E7PA15/ADC2/DEBUG/FMC/HDP/I2S4/TIM2/UART4passive
E8VSSpassive
E9PH13/DEBUG_TRACED15/I2C5_SCL/I2S3_CK/SPI3_SCK/TIM8_CH1N/UART4_TX/USART2_CKpassive
F1PH8/DEBUG_TRACED9/FMC_A8/HDP_HDP2/I2C3_SDA/TIM5_ETR/USART2_RXpassive
F2PA12/FMC_A7/SAI2_MCLK_A/TIM1_ETR/USART1_DE/USART1_RTSpassive
F3VDDpassive
F4VDDCPUpassive
F5VSSpassive
F6VDDCOREpassive
F7PD14/FMC_D0/FMC_DA0/I2C3_SDA/TIM4_CH3/UART8_CTS/USART1_RXpassive
F8PE8/DFSDM1_CKIN2/FMC_D5/FMC_DA5/I2C1_SDA/TIM1_CH1N/UART7_TXpassive
F9PB5/DEBUG_TRACED4/I2C4_SMBA/I2S2_SDI/SDMMC1_CKIN/SPI2_MISO/~{TIM17_BKIN}/TIM3_CH2/UART5_RXpassive
G1PD11/ADC2/FMC/I2C4/LPTIM2/QUADSPI/SPDIFRX/UART7/USART3passive
G2PH2/ETH1_CRS/~{FMC_NE4}/LPTIM1_IN2/~{QUADSPI_BK2_IO0}/UART7_TXpassive
G3PB6/DEBUG_TRACED6/~{FMC_NE3}/HDP_HDP6/~{QUADSPI_BK1_NCS}/SAI1_CK2/TIM16_CH1N/TIM4_CH1/TIM8_CH1/USART1_TXpassive
G4PB8/DFSDM1_DATIN1/FMC_D13/FMC_DA13/I2C1_SCL/I2C3_SCL/SAI1_D1/TIM16_CH1/TIM4_CH3/UART4_RXpassive
G5PG9/DEBUG_DBTRGO/~{FMC_NCE}/~{FMC_NE2}/I2C2_SDA/SPDIFRX_IN3/USART6_RXpassive
G6PD3/DFSDM1_CKOUT/FMC_CLK/I2C1_SDA/SAI1_D3/TIM2_CH1/TIM2_ETR/USART2_CTS/~{USART2_NSS}passive
G7PH12/DFSDM1/ETH1/FMC/I2C3/QUADSPI/SAI1/SPI5/TIM5/USART2passive
G8PG15/ADC2_EXTI15/~{QUADSPI_BK1_IO1}/UART7_CTS/USART6_CTS/~{USART6_NSS}passive
G9PD6/SAI1_D1/SAI1_SD_A/TIM16_CH1N/UART4_TXpassive
H1PG5/FMC_A15/TIM17_CH1passive
H2PG10/~{FMC_NE3}/~{QUADSPI_BK2_IO1}/~{SAI1_SD_B}/SPI5_SCK/UART8_CTSpassive
H3PF8/PWR_WKUP1/~{QUADSPI_BK1_IO0}/~{SAI1_SCK_B}/TIM13_CH1/TIM16_CH1N/TIM4_CH3/TIM8_CH3/USART6_TXpassive
H4VDDCPUpassive
H5VSSpassive
H6VDDCOREpassive
H7PH11/ADC2/FMC/I2C4/I2S2/QUADSPI/SAI2/SPI2/SPI5/TIM5/USART6passive
H8PI3/ETH1_RX_ER/PWR_WKUP2/SPDIFRX_IN3/TAMP_IN4/TAMP_OUT5passive
H9PF9/DFSDM1/FMC/QUADSPI/SAI1/TIM14/TIM17/TIM1/UART7/UART8passive
J1VDD_PLLpassive
J2VSS_PLLpassive
J3PG8/FMC/QUADSPI/SAI1/SPDIFRX/SPI5/TAMP/TIM2/TIM8/USART3passive
J4PI2/PWR_WKUP5/SPDIFRX_IN2/TAMP_IN3/TAMP_OUT4passive
J5VBATpassive
J6PH6/ETH1/I2C5/I2S2/QUADSPI/SPI2/TIM12/USART2passive
J7PF7/ETH1_CLK125/FMC_A18/TIM17_CH1/UART4_CTS/UART7_TXpassive
J8PA8/FMC/I2C4/I2S2/RCC/SAI2/SPI2/SPI5/TIM8/USART1/USBpassive
J9PF12/ETH1_CLK125/ETH1_TX_ER/I2S1_WS/SAI1_SD_A/~{SPI1_NSS}/UART4_TXpassive
K1PE4/DFSDM1/FMC/I2S/QUADSPI/SAI1/SPI5/TIM15/UART7/UART8passive
K2PF10/QUADSPI/SAI1/SPI5/TAMP/TIM16/TIM8/UART7/USART6passive
K3PB2/FMC_A6/I2S_CKIN/~{QUADSPI_BK1_NCS}/RTC_LSCO_OUT2/RTC_OUT2/SAI1_D1/SAI1_SD_A/TAMP_IN7/UART4_RXpassive
K4VDDpassive
K5VSSpassive
K6VDDCOREpassive
K7PA13/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_1/UART4_TXpassive
K8PA1/ADC2/DFSDM1/ETH1/LPTIM3/TIM15/TIM2/TIM5/USART2passive
K9PC4/ADC2/DFSDM1/ETH1/I2S1/SAI1/SAI2/SPDIFRX/TIM3/UART5passive
L1PF6/~{QUADSPI_BK1_IO2}/~{SPI5_NSS}/TIM16_CH1/UART7_RXpassive
L2VSSpassive
L3PH7/ETH1_TX_CLK/I2C3_SDA/~{QUADSPI_BK1_IO3}/~{QUADSPI_BK2_IO3}/~{SAI2_FS_B}/SPI5_SCKpassive
L4VDD_ANApassive
L5VSS_ANApassive
L6PG12/ETH1_PHY_INTN/LPTIM1_IN1/SAI2_CK2/SAI2_SCK_A/USART3_CTS/USART6_DE/USART6_RTSpassive
L7PA0/ADC2_INN3/ADC2_INP7/ETH1_CRS/~{SAI1_SD_B}/~{TIM15_BKIN}/TIM2_CH1/TIM2_ETR/TIM5_CH1/TIM8_ETR/UART5_TXpassive
L8PF11/ADC2_EXTI11/ADC2_INN4/ADC2_INP8/DFSDM1_CKIN3/SAI1_D2/SAI1_FS_A/USART2_TXpassive
L9PE5/ETH1_TXD3/~{FMC_NE1}/~{SAI2_SCK_B}/TIM15_CH1/TIM8_CH3/UART4_RXpassive
M1PC14-OSC32_IN/RCC_OSC32_INpassive
M2PC15-OSC32_OUT/ADC2_EXTI15/RCC_OSC32_OUTpassive
M3PC13/PWR_WKUP3/RTC_LSCO/RTC_LSCO_OUT1/RTC_OUT1/RTC_TS/TAMP_IN1/TAMP_OUT2passive
M4VDDpassive
M5VSSpassive
M6PB11/ADC2_EXTI11/ETH1_TX_CTL/ETH1_TX_EN/I2C5_SMBA/LPTIM1_OUT/TIM2_CH4/USART3_RXpassive
M7PA5/ETH1_PPS_OUT/I2S1_WS/SAI1_D1/SAI1_SD_A/~{SPI1_NSS}/TIM2_CH1/TIM2_ETR/TIM8_CH1N/USART2_CKpassive
M8PB0/ADC2/DEBUG/ETH1/I2S1/SAI2/TIM1/TIM3/TIM8/UART4/USART1passive
M9VDDCOREpassive
N1PD13/FMC/LPTIM2/QUADSPI/SAI1/TIM4/TIM8/USART1passive
N2VSSpassive
N3PI0/SPDIFRX_IN0/TAMP_IN8/TAMP_OUT1passive
N4PI1/PWR_WKUP4/RTC_LSCO/RTC_LSCO_OUT2/RTC_OUT2/SPDIFRX_IN1/TAMP_IN2/TAMP_OUT3passive
N5PA11/ADC2_EXTI11/ETH1_CLK/I2C5_SCL/I2S2_WS/~{SPI2_NSS}/TIM1_CH4/USART1_CTS/~{USART1_NSS}passive
N6VSSpassive
N7PA4/DFSDM1_CKIN1/ETH1_PPS_OUT/I2S1_WS/SAI1_SCK_A/~{SAI1_SCK_B}/~{SPI1_NSS}/TIM5_ETR/USART2_CKpassive
N8PB1/ADC2_INP5/DFSDM1_DATIN1/ETH1_RXD3/I2S1_CK/SPI1_SCK/TIM1_CH3N/TIM3_CH4/TIM8_CH3N/UART4_RXpassive
N9VSSpassive
P1PH0-OSC_IN/RCC_OSC_INpassive
P2PH1-OSC_OUT/RCC_OSC_OUTpassive
P3PF4/FMC_A4/USART2_RXpassive
P4PG1/~{FMC_NBL0}/I2C2_SMBA/I2S2_SDI/LPTIM1_ETR/SAI2_D2/SAI2_FS_A/SPI2_MISO/TIM4_ETRpassive
P5VSSpassive
P6VDDpassive
P7PC3/DFSDM1/ETH1/I2S1/SAI1/SPI1/TAMP/UART5passive
P8PC5/ADC2_INP10/DFSDM1_DATIN2/ETH1_RXD1/I2S_CKIN/SAI1_D4/SAI2_D4/SPDIFRX_IN3/USART2_CTS/~{USART2_NSS}passive
P9VDDpassive
R1PG11/ADC2_EXTI11/FMC_A24/I2S2_MCK/SAI2_D3/UART4_TX/USART3_TXpassive
R2PE6/FMC_A22/I2C3_SMBA/RCC_MCO_2/~{SAI1_SCK_B}/~{SAI2_SCK_B}/TIM15_CH2/~{TIM1_BKIN2}/UART4_DE/UART4_RTSpassive
R3PD7/ETH1/FMC/I2C2/I2C3/QUADSPI/RCC/SPDIFRX/USART2passive
R4PWR_CPU_ONpassive
R5PA2/ADC2_INP1/ETH1_MDIO/LPTIM4_OUT/TIM15_CH1/TIM2_CH3/TIM5_CH3/USART2_TXpassive
R6PA7/ETH1/I2S1/SAI2/SPI1/TIM14/TIM1/TIM3/TIM8/USART1passive
R7PC1/ADC2_INP2/DFSDM1_DATIN0/ETH1_CRS_DV/ETH1_GTX_CLK/ETH1_RX_DV/SAI1_D3passive
R8PA6/I2S1/SAI2/SPI1/TAMP/TIM13/TIM1/TIM3/TIM8/UART4/USART1passive
R9PG13/ADC2_INN2/ADC2_INP6/ETH1_TXD0/LPTIM1_OUT/USART6_CTS/~{USART6_NSS}passive
T1PE2/DEBUG/FMC/I2C4/SAI1/SPDIFRX/SPI5/TIM2/USART6passive
T2PH3/ETH1_COL/I2C3_SCL/~{QUADSPI_BK1_IO0}/~{QUADSPI_BK2_IO1}/SPI5_MOSIpassive
T3PF13/ADC2_INN10/ADC2_INP11/DFSDM1_DATIN3/~{SAI1_MCLK_B}/TIM2_CH1/TIM2_ETR/UART5_RX/USART2_TXpassive
T4PC0/ADC2_INN1/ADC2_INP0/I2S1_MCK/I2S1_SDO/SAI1_CK2/SAI1_SCK_A/SPI1_MOSI/TAMP_IN3/USART1_TXpassive
T5VSSApassive
T6VREF-passive
T7PA3/ETH1/I2S1/LPTIM5/PWR/SAI1/SPI1/TIM15/TIM2/TIM5/USART2passive
T8PG14/ETH1_TXD1/LPTIM1_ETR/SAI2_D1/SAI2_SD_A/USART6_TXpassive
T9USB_DP2/USBH_HS2_DP/USB_OTG_HS_DPpassive
U1VSSpassive
U2PG3/ETH1_MDIO/FMC_A13/I2C2_SDA/~{SAI2_SD_B}/~{TIM8_BKIN2}passive
U3PG2/ETH1_MDC/RCC_MCO_2/~{SAI2_MCLK_B}/~{TIM8_BKIN}passive
U4PF14/DEBUG_JTCK-SWCLKpassive
U5VDDApassive
U6VREF+passive
U7PDR_ONpassive
U8PC2/ETH1_TXD2/I2S1_WS/SAI2_CK1/SAI2_MCLK_A/~{SPI1_NSS}/~{SPI5_NSS}/USART1_DE/USART1_RTSpassive
U9USB_DM2/USBH_HS2_DM/USB_OTG_HS_DMpassive
A10PC6/DEBUG/DFSDM1/FMC/HDP/I2S3/SDMMC1/SDMMC2/TIM3/TIM8/USART6passive
A11PF0/DEBUG_TRACED13/DFSDM1_CKOUT/FMC_A0/SDMMC2_D4/USART3_CKpassive
A12PB14/DEBUG_TRACED0/SDMMC1_D4/SDMMC2_D0/TIM12_CH1/TIM1_CH2N/TIM8_CH2N/USART1_TXpassive
A13VDDSD2passive
A14VDDSD1passive
A15DDR_DQ4/DDR_DQ4passive
A16DDR_DQ0/DDR_DQ0passive
A17VSSpassive
B10PB13/DEBUG_TRACECLK/I2C4_SCL/I2S2_WS/LPTIM2_OUT/SDMMC1_D123DIR/~{SPI2_NSS}/TIM1_CH1N/UART5_TXpassive
B11PB3/DEBUG_TRACED2/I2S4_WS/SAI2_CK1/SAI2_MCLK_A/SDMMC1_D123DIR/SDMMC2_D2/~{SPI4_NSS}/TIM2_CH2/UART7_RXpassive
B12PE3/DEBUG_TRACED11/I2S4_SDI/SAI2_D4/SDMMC2_CK/SPI4_MISO/~{TIM15_BKIN}/USART3_DE/USART3_RTSpassive
B13PC12/DEBUG_TRACECLK/~{SAI2_SD_B}/SDMMC1_CK/UART7_TXpassive
B14VSSpassive
B15DDR_DQ1/DDR_DQ1passive
B16DDR_DQS0N/DDR_DQS0Npassive
B17DDR_DQS0P/DDR_DQS0Ppassive
C10PB9/DEBUG_TRACED3/I2C4_SDA/SDMMC1_CDIR/SDMMC2_D5/TIM4_CH4/UART5_TXpassive
C11PH10/DEBUG/DFSDM1/HDP/I2S2/I2S3/SAI2/SDMMC1/SPI2/TIM5/USART3passive
C12PC11/ADC2_EXTI11/DEBUG_TRACED3/I2C1_SDA/I2S3_SDO/~{SAI2_SCK_B}/SDMMC1_D3/SPI3_MOSI/UART5_RX/USART3_CKpassive
C13PC8/DEBUG/I2S3/SAI2/SDMMC1/SPI3/TIM3/TIM8/UART5/USART3/USART6passive
C14DDR_DQ2/DDR_DQ2passive
C15DDR_DQM0/DDR_DQM0passive
C16DDR_DQ3/DDR_DQ3passive
C17DDR_DQ5/DDR_DQ5passive
D10VDDpassive
D11PB15/ADC2/DFSDM1/I2S4/RTC/SAI2/SDMMC1/SDMMC2/SPI4/TIM12/TIM1/TIM8/UART7passive
D12VDDpassive
D13VSSpassive
D14VDDQ_DDRpassive
D15DDR_RESETN/DDR_RESETNpassive
D16DDR_DQ7/DDR_DQ7passive
D17DDR_DQ6/DDR_DQ6passive
E10VSSpassive
E11PB4/DEBUG_TRACED14/I2S4_CK/SAI2_CK2/SAI2_SCK_A/SDMMC2_D3/SPI4_SCK/~{TIM16_BKIN}/TIM3_CH1/USART3_CKpassive
E12VSSpassive
E13VDDQ_DDRpassive
E14VSSpassive
E15VDDQ_DDRpassive
E16VSSpassive
E17DDR_A13/DDR_A13passive
F10VDDCOREpassive
F11PC10/DEBUG_TRACED2/I2C1_SCL/I2S3_CK/~{SAI2_MCLK_B}/SDMMC1_D2/SPI3_SCK/USART3_TXpassive
F12VDDCOREpassive
F13VSSpassive
F14VDDQ_DDRpassive
F15DDR_A7/DDR_A7passive
F16DDR_A5/DDR_A5passive
F17DDR_A9/DDR_A9passive
G10PB10/I2C5_SMBA/I2S2_CK/I2S4_WS/LPTIM2_IN1/SPI2_SCK/~{SPI4_NSS}/TIM2_CH3/USART3_TXpassive
G11PD2/DEBUG_TRACED4/I2C1_SMBA/I2S3_WS/SAI2_D1/SDMMC1_CMD/~{SPI3_NSS}/TIM3_ETR/USART3_RXpassive
G12PC9/DEBUG_TRACED1/SDMMC1_D1/TIM3_CH4/TIM8_CH4/UART5_CTS/USART3_RTSpassive
G13DDR_A2/DDR_A2passive
G14~{DDR_BA2}/~{DDR_BA2}passive
G15DDR_A3/DDR_A3passive
G16DDR_A0/DDR_A0passive
G17DDR_ODT/DDR_ODTpassive
H10PG6/DEBUG_TRACED3/HDP_HDP3/SAI2_D1/SAI2_SD_A/SDMMC2_CMD/~{TIM17_BKIN}/TIM5_CH4/USART1_RXpassive
H11BYPASS_REG1V8passive
H12VDDCOREpassive
H13VSSpassive
H14VDDQ_DDRpassive
H15~{DDR_BA0}/~{DDR_BA0}passive
H16DDR_CSN/DDR_CSNpassive
H17DDR_WEN/DDR_WENpassive
J10VDDpassive
J11VDDA1V8_REGpassive
J12PA10/TIM1_CH3/USB_OTG_HS_IDpassive
J13DDR_VREF/DDR_VREFpassive
J14DDR_RASN/DDR_RASNpassive
J15DDR_A10/DDR_A10passive
J16VSSpassive
J17DDR_CASN/DDR_CASNpassive
K10NRSTpassive
K11VSS_PLL2passive
K12VDDCOREpassive
K13VSSpassive
K14VDDQ_DDRpassive
K15DDR_A15/DDR_A15passive
K16DDR_CLKP/DDR_CLKPpassive
K17DDR_CLKN/DDR_CLKNpassive
L10PF15/ADC2_EXTI15/DEBUG_JTMS-SWDIOpassive
L11VDD_PLL2passive
L12PH5/DEBUG_JTDO-SWOpassive
L13DDR_CKE/DDR_CKEpassive
L14DDR_A12/DDR_A12passive
L15DDR_A1/DDR_A1passive
L16DDR_A11/DDR_A11passive
L17DDR_A14/DDR_A14passive
M10USB_RREFpassive
M11PI6-BOOT2passive
M12VDDCOREpassive
M13VSSpassive
M14VDDQ_DDRpassive
M15DDR_A6/DDR_A6passive
M16DDR_A8/DDR_A8passive
M17~{DDR_BA1}/~{DDR_BA1}passive
N10VSSpassive
N11PI5-BOOT1passive
N12VSSpassive
N13VDDQ_DDRpassive
N14VSSpassive
N15VDDQ_DDRpassive
N16VSSpassive
N17DDR_ATO/DDR_ATOpassive
P10VDDpassive
P11PI4-BOOT0passive
P12VDDpassive
P13VSSpassive
P14VDDQ_DDRpassive
P15DDR_A4/DDR_A4passive
P16DDR_ZQ/DDR_ZQpassive
P17DDR_DQ8/DDR_DQ8passive
R10NJTRST/DEBUG_JTRSTpassive
R11PA14/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_2/USB_OTG_HS_SOFpassive
R12VSSpassive
R13PWR_ONpassive
R14DDR_DQM1/DDR_DQM1passive
R15DDR_DQ12/DDR_DQ12passive
R16DDR_DQ11/DDR_DQ11passive
R17DDR_DQ9/DDR_DQ9passive
T10VSSpassive
T11VSS_USBHSpassive
T12USB_DP1/USBH_HS1_DPpassive
T13PH4/DEBUG_JTDIpassive
T14DDR_DQ13/DDR_DQ13passive
T15DDR_DQ14/DDR_DQ14passive
T16DDR_DQS1P/DDR_DQS1Ppassive
T17DDR_DQS1N/DDR_DQS1Npassive
U10VDDA1V1_REGpassive
U11VDD3V3_USBHSpassive
U12USB_DM1/USBH_HS1_DMpassive
U13PI7/USB_OTG_HS_VBUSpassive
U14PWR_LPpassive
U15DDR_DQ15/DDR_DQ15passive
U16DDR_DQ10/DDR_DQ10passive
U17VSSpassive

Provenance

Credit
Celestial Altium Library by Issus and contributors (https://github.com/issus/altium-library)
Licence
LicenseRef-Celestial-Altium
Link method
none
Cross-check
not confirmed