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ST MICROELECTRONICS STM32MP135C_3

celestial-altium-MCU_STM32

Symbol

320 pins
Schematic symbol for ST MICROELECTRONICS STM32MP135C_3
Units
10
Kind
part
Grid
on 1.27 mm

Footprint

none
no footprint linked

This symbol carries no usable footprint reference, so nothing is linked. Generating one is a better answer than guessing.

3D model

none
no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

No footprint is linked, so there is nothing to cross-check.

PinNameType
A1VSSpassive
A2PA9/DCMIPP_D0/DFSDM1_DATIN0/~{FMC_NWAIT}/I2C3_SMBA/LTDC_R6/TIM1_CH2/UART4_TX/USART1_TXpassive
A3PE13/DCMIPP_D4/FMC_D10/FMC_DA10/I2C5_SDA/I2S4_SDI/~{LTDC_B1}/LTDC_R6/SPI4_MISO/TIM1_CH3passive
A4PE12/DCMIPP/FMC/HDP/I2S4/LTDC/SPI4/TIM1/UART8passive
A6PD12/DCMIPP_D6/FMC_A17/FMC_ALE/I2C1_SCL/LPTIM1_IN1/TIM4_CH1/USART3_DE/USART3_RTSpassive
A7PG0/DCMIPP_PIXCLK/FDCAN2_TX/FMC_A10/LTDC_G5passive
A9PE15/ADC1/ADC2/DCMIPP/FMC/HDP/I2C4/LTDC/TIM1/TIM2/USART2passive
B1PD0/DCMIPP_D1/FDCAN1_RX/FMC_D2/FMC_DA2/SAI1_CK1/SAI1_MCLK_Apassive
B2PE11/ADC1/ADC2/DCMIPP/ETH1/ETH2/FMC/I2S4/LTDC/SAI1/SPI4/TIM1/USART2/USART6passive
B3PF5/DCMIPP_D11/DEBUG_TRACED12/DFSDM1_CKIN0/FMC_A5/I2C1_SMBA/LTDC_G0/LTDC_R5passive
B4PA15/ADC1/ADC2/DCMIPP/DEBUG/FMC/HDP/I2S4/LTDC/TIM2/UART4passive
B5PD8/DCMIPP_D3/DCMIPP_D9/I2S4_WS/UART4_RX/USART2_TX/USART3_TXpassive
B6PE0/DCMIPP_D1/DCMIPP_D12/FDCAN2_RX/FMC_A11/~{LTDC_B1}/~{LTDC_B5}/UART8_RXpassive
B7PE9/DCMIPP_D7/FMC_D6/FMC_DA6/HDP_HDP3/LTDC_HSYNC/LTDC_R7/~{QUADSPI_BK1_IO1}/TIM1_CH1passive
B8PH14/DCMIPP_D2/DCMIPP_D8/DCMIPP_PIXCLK/DFSDM1_DATIN2/I2C3_SDA/~{LTDC_B4}/UART4_RXpassive
B9PE8/DFSDM1_CKIN2/FMC_D5/FMC_DA5/I2C1_SDA/TIM1_CH1N/UART7_TXpassive
C1PB6/DCMIPP/DEBUG/ETH2/FMC/HDP/LTDC/QUADSPI/SAI1/TIM16/TIM4/TIM8/USART1passive
C2PD3/DCMIPP_D5/DFSDM1_CKOUT/FMC_CLK/I2C1_SDA/SAI1_D3/TIM2_CH1/TIM2_ETR/USART2_CTS/~{USART2_NSS}passive
C3PE14/DCMIPP/FMC/LTDC/QUADSPI/SAI1/TAMP/TIM1/UART8passive
C4PD14/DCMIPP_D8/FMC_D0/FMC_DA0/I2C3_SDA/LTDC_R4/TIM4_CH3/UART8_CTS/USART1_RXpassive
C5PD1/DCMIPP_D13/FMC_D3/FMC_DA3/I2C5_SCL/I2S4_SDO/~{LTDC_B6}/LTDC_G2/~{QUADSPI_BK1_NCS}/SPI4_MOSI/UART4_TXpassive
C6PB7/DCMIPP_D13/DCMIPP_PIXCLK/~{FMC_NCE2}/~{FMC_NL}/I2C4_SDA/I2S4_CK/TIM17_CH1N/TIM4_CH2passive
C7PD4/DFSDM1_CKIN0/~{FMC_NOE}/I2S3_SDI/LTDC_R1/LTDC_R4/LTDC_R6/QUADSPI_CLK/SPI3_MISO/USART2_DE/USART2_RTSpassive
C8PD5/~{FMC_NWE}/~{LTDC_B0}/LTDC_G4/~{QUADSPI_BK1_IO0}passive
C9PD9/DEBUG_TRACECLK/DFSDM1_DATIN3/FMC_D14/FMC_DA14/~{LTDC_B0}/~{LTDC_B5}/LTDC_CLK/SDMMC2_CDIRpassive
D1PB8/DCMIPP_D6/DFSDM1_DATIN1/FMC_D13/FMC_DA13/I2C1_SCL/I2C3_SCL/SAI1_D1/TIM16_CH1/TIM4_CH3/UART4_RXpassive
D2PD6/DCMIPP_D0/DCMIPP_D4/SAI1_D1/SAI1_SD_A/TIM16_CH1N/UART4_TXpassive
D3PH12/DCMIPP/DFSDM1/ETH1/FMC/I2C3/QUADSPI/SAI1/SPI5/TIM5/USART2passive
D6PD10/DCMIPP/FMC/I2C5/I2S4/LTDC/RTC/SPI4/USART3passive
D8PE7/FMC_D4/FMC_DA4/LPTIM2_IN1/~{LTDC_B3}/LTDC_R5/TIM1_ETR/UART5_TXpassive
E2PH2/DCMIPP/ETH1/ETH2/FMC/LPTIM1/LTDC/QUADSPI/UART7passive
E3PH8/DCMIPP_HSYNC/DEBUG_TRACED9/FMC_A8/HDP_HDP2/I2C3_SDA/LTDC_R2/LTDC_R6/TIM5_ETR/USART2_RXpassive
E5VSSpassive
E6VSSpassive
E7VDDCPUpassive
E8PE1/DCMIPP_D3/DCMIPP_D12/~{FMC_NBL1}/LPTIM1_IN2/LTDC_HSYNC/LTDC_R4/UART8_TXpassive
E9PD15/ADC1_EXTI15/ADC2_EXTI15/DFSDM1_DATIN2/FMC_D1/FMC_DA1/~{LTDC_B5}/~{QUADSPI_BK1_IO3}/TIM4_CH4/USART2_RXpassive
F1PF8/DCMIPP/LTDC/PWR/QUADSPI/SAI1/TIM13/TIM16/TIM4/TIM8/USART6passive
F2PG9/DCMIPP_VSYNC/DEBUG_DBTRGO/FDCAN1_RX/~{FMC_NCE}/~{FMC_NE2}/I2C2_SDA/SPDIFRX_IN3/USART6_RXpassive
F3PD11/ADC1/ADC2/DCMIPP/ETH2/FMC/I2C4/LPTIM2/LTDC/QUADSPI/SPDIFRX/UART7/USART3passive
F4PA12/DCMIPP/ETH2/FMC/LTDC/SAI2/TIM1/USART1passive
F5VSSpassive
G1PF6/ETH2_TX_CTL/ETH2_TX_EN/LTDC_G4/LTDC_R7/~{QUADSPI_BK1_IO2}/~{SPI5_NSS}/TIM16_CH1/UART7_RXpassive
G2PG10/DCMIPP_D2/FDCAN1_TX/~{FMC_NE3}/~{QUADSPI_BK2_IO1}/~{SAI1_SD_B}/SPI5_SCK/UART8_CTSpassive
G3PG5/DCMIPP_D3/DCMIPP_VSYNC/ETH2_MDC/FMC_A15/LTDC_G4/TIM17_CH1passive
G5VDDCPUpassive
G7VDDCPUpassive
G8VSSpassive
G9VDDpassive
H2PE4/DCMIPP/DFSDM1/FMC/I2S/LTDC/QUADSPI/SAI1/SPI5/TIM15/UART7/UART8passive
H3PF10/DCMIPP/LTDC/QUADSPI/SAI1/SPI5/TAMP/TIM16/TIM8/UART7/USART6passive
H4PG15/ADC1/ADC2/DCMIPP/ETH2/LTDC/QUADSPI/UART7/USART6passive
H5PG8/DCMIPP/ETH2/FMC/LTDC/QUADSPI/SAI1/SPDIFRX/SPI5/TAMP/TIM2/TIM8/USART3passive
H7VSSpassive
J1PH7/ETH1_TX_CLK/ETH2_TX_CLK/I2C3_SDA/~{LTDC_B2}/~{QUADSPI_BK1_IO3}/~{QUADSPI_BK2_IO3}/~{SAI2_FS_B}/SPI5_SCKpassive
J2PD13/FMC/LPTIM2/LTDC/QUADSPI/SAI1/TIM4/TIM8/USART1passive
J3PB2/ETH2/FMC/I2S/LTDC/QUADSPI/RTC/SAI1/TAMP/UART4passive
J5PF9/DFSDM1/FMC/LTDC/QUADSPI/SAI1/TIM14/TIM17/TIM1/UART7/UART8passive
J7VDDpassive
J9VDDpassive
K1VSS_PLLpassive
K2VDD_PLLpassive
K3PH11/ADC1/ADC2/ETH2/FMC/I2C4/I2S2/LTDC/QUADSPI/SAI2/SPI2/SPI5/TIM5/USART6passive
K5VDDCPUpassive
K7VDDCPUpassive
K9VSSpassive
L2VBATpassive
L3PC15-OSC32_OUT/ADC1_EXTI15/ADC2_EXTI15/RCC_OSC32_OUTpassive
L4PI3/ETH1_RX_ER/PWR_WKUP2/SPDIFRX_IN3/TAMP_IN4/TAMP_OUT5passive
L5VSSpassive
L7VDDCOREpassive
L9VDDCOREpassive
M1VSSpassive
M2PC14-OSC32_IN/RCC_OSC32_INpassive
M3PC13/PWR_WKUP3/RTC_LSCO/RTC_LSCO_OUT1/RTC_OUT1/RTC_TS/TAMP_IN1/TAMP_OUT2passive
M5VDDpassive
M7VSSpassive
M9VSSpassive
N1PE2/DEBUG/ETH2/FMC/I2C4/LTDC/SAI1/SPDIFRX/SPI5/TIM2/USART6passive
N2PF4/DCMIPP_D4/ETH2_RXD0/FMC_A4/~{LTDC_B6}/USART2_RXpassive
N3PH6/ETH1/ETH2/I2C5/I2S2/QUADSPI/SPI2/TIM12/USART2passive
N5PI2/PWR_WKUP5/SPDIFRX_IN2/TAMP_IN3/TAMP_OUT4passive
N7VDDpassive
N9VDDpassive
P2PA8/ETH2/FMC/I2C4/I2S2/LTDC/RCC/SAI2/SPI2/SPI5/TIM8/USART1/USBpassive
P3PF7/ETH1_CLK125/ETH2_TXD0/FMC_A18/LTDC_G2/TIM17_CH1/UART4_CTS/UART7_TXpassive
P4PI1/PWR_WKUP4/RTC_LSCO/RTC_LSCO_OUT2/RTC_OUT2/SPDIFRX_IN1/TAMP_IN2/TAMP_OUT3passive
P5PI0/SPDIFRX_IN0/TAMP_IN8/TAMP_OUT1passive
P7VSSpassive
R1PG1/ETH2/FDCAN2/FMC/I2C2/I2S2/LPTIM1/LTDC/SAI2/SPI2/TIM4passive
R2PG11/ADC1/ADC2/DCMIPP/ETH2/FMC/I2S2/LTDC/SAI2/UART4/USART3passive
R3PH3/ETH1_COL/ETH2_COL/I2C3_SCL/~{LTDC_B4}/LTDC_R5/~{QUADSPI_BK1_IO0}/~{QUADSPI_BK2_IO1}/SPI5_MOSIpassive
R5VDDpassive
R7VDDpassive
R8VSSpassive
R9VDDpassive
T1VSSpassive
T2PE6/DCMIPP/ETH2/FMC/I2C3/LTDC/RCC/SAI1/SAI2/TIM15/TIM1/UART4passive
T3PH0-OSC_IN/RCC_OSC_INpassive
T4PA13/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_1/UART4_TXpassive
T5VSSpassive
U2PH1-OSC_OUT/RCC_OSC_OUTpassive
U3VSS_ANApassive
U5VSSpassive
U6VSSpassive
U7VDDpassive
U8VDDApassive
U9VSSApassive
V1PD7/ETH1/FMC/I2C2/I2C3/QUADSPI/RCC/SPDIFRX/USART2passive
V2VDD_ANApassive
V3PG2/DCMIPP_D1/ETH1_MDC/RCC_MCO_2/~{SAI2_MCLK_B}/~{TIM8_BKIN}passive
V6PA7/ADC1/ETH1/I2S1/SAI2/SPI1/TIM14/TIM1/TIM3/TIM8/USART1passive
V8VREF-passive
W1PG3/DCMIPP_D12/DCMIPP_D15/ETH1_MDIO/ETH2_GTX_CLK/FDCAN2_RX/FMC_A13/I2C2_SDA/~{SAI2_SD_B}/~{TIM8_BKIN2}passive
W2PG12/ETH1/ETH2/LPTIM1/SAI2/USART3/USART6passive
W3PWR_CPU_ONpassive
W4PF13/ADC1/ADC2/DFSDM1/SAI1/TIM2/UART5/USART2passive
W5PC0/ADC1/ADC2/I2S1/SAI1/SPI1/TAMP/USART1passive
W6PC3/ADC1/DFSDM1/ETH1/ETH2/I2S1/SAI1/SPI1/TAMP/UART5passive
W7VREF+passive
W8PB0/ADC1/ADC2/DEBUG/ETH1/I2S1/SAI2/TIM1/TIM3/TIM8/UART4/USART1passive
W9PA3/ADC1/ETH1/ETH2/I2S1/LPTIM5/PWR/SAI1/SPI1/TIM15/TIM2/TIM5/USART2passive
Y1PA11/ADC1/ADC2/ETH1/ETH2/I2C5/I2S2/SPI2/TIM1/USART1passive
Y2PF14/DEBUG_JTCK-SWCLKpassive
Y3PA0/ADC1/ADC2/ETH1/ETH2/SAI1/TIM15/TIM2/TIM5/TIM8/UART5passive
Y4PA2/ADC1_INP1/ADC2_INP1/ETH1_MDIO/LPTIM4_OUT/TIM15_CH1/TIM2_CH3/TIM5_CH3/USART2_TXpassive
Y5PA5/ADC1/ETH1/ETH2/I2S1/SAI1/SPI1/TIM2/TIM8/USART2passive
Y6PF11/ADC1/ADC2/DFSDM1/ETH2/SAI1/USART2passive
Y7PC4/ADC1/ADC2/DFSDM1/ETH1/I2S1/SAI1/SAI2/SPDIFRX/TIM3/UART5passive
Y8PB1/ADC1/ADC2/DFSDM1/ETH1/I2S1/SPI1/TIM1/TIM3/TIM8/UART4passive
Y9PC1/ADC2_INP2/DFSDM1_DATIN0/ETH1_CRS_DV/ETH1_GTX_CLK/ETH1_RX_DV/SAI1_D3passive
A10PG7/DEBUG_TRACED8/I2S3_SDI/LTDC_R1/LTDC_R2/LTDC_R5/SDMMC2_CKIN/SPI3_MISO/TIM1_ETR/UART7_CTSpassive
A12PH13/DEBUG_TRACED15/I2C5_SCL/I2S3_CK/LTDC_G2/LTDC_G3/SPI3_SCK/TIM8_CH1N/UART4_TX/USART2_CKpassive
A13PF3/FMC_A3/I2C5_SDA/I2S3_WS/I2S4_SDI/LPTIM2_IN2/LTDC_G3/~{SPI3_NSS}/SPI4_MISOpassive
A15PB9/DEBUG_TRACED3/FDCAN1_TX/I2C4_SDA/~{LTDC_B1}/LTDC_DE/SDMMC1_CDIR/SDMMC2_D5/TIM4_CH4/UART5_TXpassive
A16PF0/DEBUG_TRACED13/DFSDM1_CKOUT/FMC_A0/LTDC_G0/LTDC_R6/SDMMC2_D4/USART3_CKpassive
A18PC10/DEBUG_TRACED2/I2C1_SCL/I2S3_CK/~{SAI2_MCLK_B}/SDMMC1_D2/SPI3_SCK/USART3_TXpassive
A19PC12/DEBUG_TRACECLK/LTDC_DE/~{SAI2_SD_B}/SDMMC1_CK/UART7_TXpassive
A20PC9/DEBUG_TRACED1/FDCAN1_TX/~{LTDC_B4}/SDMMC1_D1/TIM3_CH4/TIM8_CH4/UART5_CTS/USART3_RTSpassive
A21VSSpassive
AA1VSSpassive
AA2PB11/ADC1_EXTI11/ADC2_EXTI11/ETH1_TX_CTL/ETH1_TX_EN/I2C5_SMBA/LPTIM1_OUT/TIM2_CH4/USART3_RXpassive
AA3PA1/ADC1/ADC2/DFSDM1/ETH1/LPTIM3/TIM15/TIM2/TIM5/USART2passive
AA4PF12/ADC1_INN2/ADC1_INP6/ETH1_CLK125/ETH1_TX_ER/I2S1_WS/SAI1_SD_A/~{SPI1_NSS}/UART4_TXpassive
AA6PA4/ADC1/DFSDM1/ETH1/ETH2/I2S1/SAI1/SPI1/TIM5/USART2passive
AA7PC5/ADC1/ADC2/DFSDM1/ETH1/I2S/SAI1/SAI2/SPDIFRX/USART2passive
AA9PG13/ADC2_INN2/ADC2_INP6/ETH1_TXD0/LPTIM1_OUT/USART6_CTS/~{USART6_NSS}passive
B10PG4/DCMIPP/DEBUG/DFSDM1/FMC/HDP/LTDC/SDMMC2/TIM1/USART3passive
B11PF1/DEBUG_TRACED7/FMC_A1/HDP_HDP7/I2C2_SDA/I2S3_SDO/~{LTDC_B7}/LTDC_G1/SPI3_MOSIpassive
B12VSSpassive
B13PB5/DEBUG/FDCAN2/I2C4/I2S2/LTDC/SDMMC1/SPI2/TIM17/TIM3/UART5passive
B14PC6/DEBUG/DFSDM1/FMC/HDP/I2S3/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6passive
B15PB15/ADC1/ADC2/DFSDM1/I2S4/LTDC/RTC/SAI2/SDMMC1/SDMMC2/SPI4/TIM12/TIM1/TIM8/UART7passive
B16PB14/DEBUG_TRACED0/LTDC_G5/LTDC_R0/SDMMC1_D4/SDMMC2_D0/TIM12_CH1/TIM1_CH2N/TIM8_CH2N/USART1_TXpassive
B17PE3/DEBUG/FDCAN1/I2S4/LTDC/SAI2/SDMMC2/SPI4/TIM15/USART3passive
B18PC11/ADC1/ADC2/DEBUG/I2C1/I2S3/SAI2/SDMMC1/SPI3/UART5/USART3passive
B19DDR_DQ4/DDR_DQ4passive
B20DDR_DQ1/DDR_DQ1passive
B21DDR_DQ0/DDR_DQ0passive
C10PE10/FDCAN1_TX/FMC_D7/FMC_DA7/TIM1_CH2N/UART7_RXpassive
C11PB12/DEBUG/DFSDM1/I2C2/LTDC/SDMMC1/UART5/UART7/USART3passive
C12PH9/DCMIPP_D8/DCMIPP_D9/DCMIPP_D13/FMC_A20/I2S4_CK/~{LTDC_B5}/LTDC_DE/SPI4_SCK/TIM12_CH2/TIM1_CH4passive
C13PC7/DEBUG/HDP/I2S2/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART3/USART6passive
C14PB3/DEBUG/I2S4/LTDC/SAI2/SDMMC1/SDMMC2/SPI4/TIM2/UART7passive
C15VDDSD2passive
C16PB4/DEBUG/I2S4/LTDC/SAI2/SDMMC2/SPI4/TIM16/TIM3/USART3passive
C17PG6/DEBUG/HDP/LTDC/SAI2/SDMMC2/TIM17/TIM5/USART1passive
C18PC8/DEBUG/I2S3/LTDC/SAI2/SDMMC1/SPI3/TIM3/TIM8/UART5/USART3/USART6passive
C19PD2/DEBUG_TRACED4/I2C1_SMBA/I2S3_WS/SAI2_D1/SDMMC1_CMD/~{SPI3_NSS}/TIM3_ETR/USART3_RXpassive
C20DDR_DQS0P/DDR_DQS0Ppassive
C21DDR_DQS0N/DDR_DQS0Npassive
D11PF2/DEBUG_TRACED1/DFSDM1_CKIN1/FMC_A2/I2C2_SCL/~{LTDC_B3}/LTDC_G4/SDMMC1_D0DIR/SDMMC2_D0DIR/USART6_CKpassive
D14PB13/DEBUG/FDCAN2/I2C4/I2S2/LPTIM2/LTDC/SDMMC1/SPI2/TIM1/UART5passive
D16VSSpassive
D19DDR_DQ2/DDR_DQ2passive
D20DDR_DQ5/DDR_DQ5passive
D21DDR_DQM0/DDR_DQM0passive
E10VDDCPUpassive
E11VSSpassive
E12VDDpassive
E13PB10/I2C5_SMBA/I2S2_CK/I2S4_WS/LPTIM2_IN1/LTDC_R3/SPI2_SCK/~{SPI4_NSS}/TIM2_CH3/USART3_TXpassive
E14PH10/DEBUG/DFSDM1/HDP/I2S2/I2S3/LTDC/SAI2/SDMMC1/SPI2/TIM5/USART3passive
E15VDDQ_DDRpassive
E16VSSpassive
E17VDDSD1passive
E19DDR_DQ3/DDR_DQ3passive
E20DDR_DQ6/DDR_DQ6passive
F17VSSpassive
F18VSSpassive
F19DDR_DQ7/DDR_DQ7passive
F20DDR_A5/DDR_A5passive
F21VSSpassive
G10VDDCPUpassive
G11VDDCOREpassive
G12VSSpassive
G13VDDpassive
G14VSSpassive
G15VDDQ_DDRpassive
G17VDDQ_DDRpassive
G19DDR_A13/DDR_A13passive
G20DDR_A2/DDR_A2passive
G21DDR_A9/DDR_A9passive
H15VSSpassive
H17DDR_RESETN/DDR_RESETNpassive
H18~{DDR_BA2}/~{DDR_BA2}passive
H19DDR_A3/DDR_A3passive
H20DDR_A0/DDR_A0passive
J10VSSpassive
J11VDDCOREpassive
J12VSSpassive
J13VDDpassive
J15VDDCOREpassive
J17DDR_A7/DDR_A7passive
J19~{DDR_BA0}/~{DDR_BA0}passive
J20DDR_CSN/DDR_CSNpassive
J21DDR_ODT/DDR_ODTpassive
K10VSSpassive
K11VSSpassive
K12VSSpassive
K13VSSpassive
K15VDDQ_DDRpassive
K17VDDQ_DDRpassive
K19DDR_WEN/DDR_WENpassive
K20DDR_RASN/DDR_RASNpassive
K21VSSpassive
L10VSSpassive
L12VSSpassive
L13VDDCOREpassive
L15VSSpassive
L17VSSpassive
L18DDR_A10/DDR_A10passive
L19DDR_CASN/DDR_CASNpassive
L20DDR_CLKN/DDR_CLKNpassive
M10VSSpassive
M11VSSpassive
M12VSSpassive
M13VSSpassive
M15VDDQ_DDRpassive
M17VDDQ_DDRpassive
M19DDR_A12/DDR_A12passive
M20DDR_CLKP/DDR_CLKPpassive
M21DDR_A15/DDR_A15passive
N10VDDCOREpassive
N11VSSpassive
N12VDDpassive
N13VDDCOREpassive
N15VDDCOREpassive
N17DDR_A11/DDR_A11passive
N19DDR_A14/DDR_A14passive
N20DDR_CKE/DDR_CKEpassive
N21DDR_A1/DDR_A1passive
P15VSSpassive
P17DDR_DTO1/DDR_DTO1passive
P18DDR_ATO/DDR_ATOpassive
P19DDR_A8/DDR_A8passive
P20~{DDR_BA1}/~{DDR_BA1}passive
R10VDDCOREpassive
R11VSSpassive
R12VDDpassive
R13VDDCOREpassive
R14VSSpassive
R15VDDQ_DDRpassive
R17VDDQ_DDRpassive
R19DDR_A4/DDR_A4passive
R20DDR_ZQ/DDR_ZQpassive
R21DDR_A6/DDR_A6passive
T17VSSpassive
T18DDR_VREF/DDR_VREFpassive
T19DDR_DQ10/DDR_DQ10passive
T20DDR_DQ8/DDR_DQ8passive
T21VSSpassive
U10PA6/ADC1/I2S1/SAI2/SPI1/TAMP/TIM13/TIM1/TIM3/TIM8/UART4/USART1passive
U11VSSpassive
U12VDDCOREpassive
U13VSSpassive
U14VDDCOREpassive
U15VDDQ_DDRpassive
U16VSSpassive
U17PWR_ONpassive
U19DDR_DQ13/DDR_DQ13passive
U20DDR_DQ9/DDR_DQ9passive
V11NJTRST/DEBUG_JTRSTpassive
V14VDDA1V1_REGpassive
V16VSSpassive
V19PWR_LPpassive
V20DDR_DQS1P/DDR_DQS1Ppassive
V21DDR_DQS1N/DDR_DQS1Npassive
W10PE5/ETH1_TXD3/~{FMC_NE1}/~{SAI2_SCK_B}/TIM15_CH1/TIM8_CH3/UART4_RXpassive
W11VDDpassive
W12USB_RREFpassive
W13PA14/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_2/USB_OTG_HS_SOFpassive
W14VDD3V3_USBHSpassive
W15VDDA1V8_REGpassive
W16VSSpassive
W17BYPASS_REG1V8passive
W18PH5/DEBUG_JTDO-SWOpassive
W19DDR_DQ12/DDR_DQ12passive
W20DDR_DQ11/DDR_DQ11passive
W21DDR_DQM1/DDR_DQM1passive
Y10PG14/ETH1_TXD1/LPTIM1_ETR/SAI2_D1/SAI2_SD_A/USART6_TXpassive
Y11NRSTpassive
Y12PF15/ADC1_EXTI15/ADC2_EXTI15/DEBUG_JTMS-SWDIOpassive
Y13USB_DM2/USBH_HS2_DM/USB_OTG_HS_DMpassive
Y14VSS_USBHSpassive
Y15PI6-BOOT2passive
Y16USB_DP1/USBH_HS1_DPpassive
Y17PI4-BOOT0passive
Y18VDD_PLL2passive
Y19PH4/DEBUG_JTDIpassive
Y20DDR_DQ15/DDR_DQ15passive
Y21DDR_DQ14/DDR_DQ14passive
AA10PC2/ADC1_INP15/ETH1_TXD2/I2S1_WS/SAI2_CK1/SAI2_MCLK_A/~{SPI1_NSS}/~{SPI5_NSS}/USART1_DE/USART1_RTSpassive
AA12PDR_ONpassive
AA13USB_DP2/USBH_HS2_DP/USB_OTG_HS_DPpassive
AA15PI5-BOOT1passive
AA16USB_DM1/USBH_HS1_DMpassive
AA18VSS_PLL2passive
AA19PA10/TIM1_CH3/USB_OTG_HS_IDpassive
AA20PI7/USB_OTG_HS_VBUSpassive
AA21VSSpassive

Provenance

Credit
Celestial Altium Library by Issus and contributors (https://github.com/issus/altium-library)
Licence
LicenseRef-Celestial-Altium
Link method
none
Cross-check
not confirmed