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ST MICROELECTRONICS STM32MP153C_2

celestial-altium-MCU_STM32

Symbol

257 pins
Schematic symbol for ST MICROELECTRONICS STM32MP153C_2
Units
8
Kind
part
Grid
on 1.27 mm

Footprint

none
no footprint linked

This symbol carries no usable footprint reference, so nothing is linked. Generating one is a better answer than guessing.

3D model

none
no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

No footprint is linked, so there is nothing to cross-check.

PinNameType
A1VSSpassive
A2PD1/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4passive
A3PB7/DCMI_VSYNC/DFSDM1_CKIN5/~{FMC_NL}/I2C1_SDA/I2C4_SDA/SDMMC2_D1/TIM17_CH1N/TIM4_CH2/USART1_RXpassive
A4PC6/DCMI/DFSDM1/HDP/I2S2/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6passive
A6VSSpassive
A7PD3/DCMI/DFSDM1/FMC/HDP/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/USART2passive
A9PC8/DCMI_D2/DEBUG_TRACED0/SDMMC1_D0/TIM3_CH3/TIM8_CH3/UART4_TX/UART5_DE/UART5_RTS/USART6_CKpassive
B1PG15/ADC1/ADC2/DCMI/DEBUG/I2C2/SAI1/SDMMC3/USART6passive
B2PE6/DCMI/DEBUG/FMC/LTDC/SAI1/SAI2/SDMMC1/SDMMC2/SPI4/TIM15/TIM1passive
B3PD7/DEBUG_TRACED6/DFSDM1_CKIN1/DFSDM1_DATIN4/~{FMC_NE1}/I2C2_SCL/SDMMC3_D3/SPDIFRX_IN0/USART2_CKpassive
B4PA15/CEC/ADC1/ADC2/DEBUG/I2S1/I2S3/LTDC/SAI4/SDMMC1/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART4/UART7passive
B5PG6/DCMI_D12/DEBUG_TRACED14/LTDC_R7/SDMMC2_CMD/~{TIM17_BKIN}passive
B6PB4/DEBUG/I2S1/I2S2/I2S3/SAI4/SDMMC2/SPI1/SPI2/SPI3/SPI6/TIM16/TIM3/UART7passive
B7PE5/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15passive
B8PA8/I2C3/I2S3/LTDC/RCC/SAI4/SDMMC2/SPI3/TIM1/TIM8/UART7/USART1/USBpassive
B9PC9/DAC1/DCMI/DEBUG/I2C3/I2S/LTDC/QUADSPI/SDMMC1/TIM3/TIM8/UART5passive
C1PE12/DFSDM1_DATIN5/FMC_D9/FMC_DA9/~{LTDC_B4}/~{SAI2_SCK_B}/SDMMC1_D0DIR/SPI4_SCK/TIM1_CH3Npassive
C2PE0/DCMI/FMC/I2S3/LPTIM1/LPTIM2/SAI2/SAI4/SPI3/TIM4/UART8passive
C3PD4/DFSDM1_CKIN0/~{FMC_NOE}/SAI3_FS_A/SDMMC3_D1/USART2_DE/USART2_RTSpassive
C4PD5/~{FMC_NWE}/SDMMC3_D2/USART2_TXpassive
C5PD0/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4passive
C6PA9/DAC1_EXTI9/DCMI_D0/I2C3_SMBA/I2S2_CK/LTDC_R5/SDMMC2_CDIR/SDMMC2_D5/SPI2_SCK/TIM1_CH2/USART1_TXpassive
C7PB3/DEBUG/I2S1/I2S3/SAI4/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART7passive
C8PB15/ADC1/ADC2/DFSDM1/I2S2/RTC/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1passive
C9PB9/DAC1/DCMI/DFSDM1/FDCAN1/HDP/I2C1/I2C4/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/TIM17/TIM4/UART4passive
D1PG12/ETH1/FMC/LPTIM1/LTDC/SAI4/SPDIFRX/SPI6/USART6passive
D2PE11/ADC1/ADC2/DCMI/DFSDM1/FMC/LTDC/SAI2/SPI4/TIM1/USART6passive
D3PE15/ADC1/ADC2/FMC/HDP/LTDC/TIM15/TIM1/UART8/USART2passive
E1PD8/DFSDM1_CKIN3/FMC_D13/FMC_DA13/~{LTDC_B7}/~{SAI3_SCK_B}/SPDIFRX_IN1/USART3_TXpassive
E2NRSTpassive
E3PE13/DCMI_D6/DFSDM1_CKIN5/FMC_D10/FMC_DA10/HDP_HDP2/LTDC_DE/~{SAI2_FS_B}/SPI4_MISO/TIM1_CH3passive
F2PC15-OSC32_OUT/ADC1_EXTI15/ADC2_EXTI15/RCC_OSC32_OUTpassive
F3VSSpassive
G1VSSpassive
G2PC14-OSC32_IN/RCC_OSC32_INpassive
G3PC13/PWR_WKUP3/RTC_LSCO/RTC_TS/TAMP_IN1/TAMP_OUT2/TAMP_OUT3passive
H1BOOT2passive
H2PH0-OSC_IN/RCC_OSC_INpassive
H3BOOT0passive
J2PH1-OSC_OUT/RCC_OSC_OUTpassive
J3NRST_COREpassive
K1PWR_LPpassive
K2PDR_ON_COREpassive
K3BOOT1passive
L1PA14/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_2passive
L2PA13/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_1/UART4_TXpassive
L3PDR_ONpassive
M2PWR_ONpassive
M3VREF+passive
N1VSSpassive
N2PA3/ADC1_INP15/ETH1_COL/LPTIM5_OUT/~{LTDC_B2}/~{LTDC_B5}/PWR_PVD_IN/TIM15_CH2/TIM2_CH4/TIM5_CH4/USART2_RXpassive
N3PA0/ADC1/ETH1/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/TIM8/UART4/USART2passive
P1PE2/DEBUG_TRACECLK/ETH1_TXD3/FMC_A23/I2C4_SCL/~{QUADSPI_BK1_IO2}/SAI1_CK1/SAI1_MCLK_A/SPI4_SCKpassive
P2PC2/ADC1_INN11/ADC1_INP12/DCMI_PIXCLK/DFSDM1_CKIN1/DFSDM1_CKOUT/ETH1_TXD2/I2S2_SDI/SPI2_MISOpassive
P3PC3/ADC1_INN12/ADC1_INP13/DEBUG_TRACECLK/DFSDM1_DATIN1/ETH1_TX_CLK/I2S2_SDO/SPI2_MOSIpassive
R2PG14/DEBUG/ETH1/FMC/LPTIM1/LTDC/QUADSPI/SAI4/SPI6/USART6passive
R3PG13/DEBUG/ETH1/FMC/LPTIM1/LTDC/SAI1/SAI4/SPI6/USART6passive
T1PA1/ADC1/ETH1/LPTIM3/LTDC/QUADSPI/SAI2/TIM15/TIM2/TIM5/UART4/USART2passive
T2PC1/ADC1/ADC2/DEBUG/DFSDM1/ETH1/I2S2/PWR/SAI1/SDMMC2/SPI2/TAMPpassive
T3PA2/ADC1/ETH1/LPTIM4/LTDC/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/USART2passive
U1PB1/ADC1_INP5/ADC2_INP5/DFSDM1_DATIN1/ETH1_RXD3/LTDC_G0/LTDC_R6/TIM1_CH3N/TIM3_CH4/TIM8_CH3Npassive
U2PB0/ADC1/ADC2/DFSDM1/ETH1/LTDC/TIM1/TIM3/TIM8/UART4passive
U3PB11/ADC1/ADC2/DFSDM1/ETH1/I2C2/LPTIM2/LTDC/TIM2/USART3passive
U4PC0/ADC1_INP10/ADC2_INP10/DFSDM1_CKIN0/DFSDM1_DATIN4/LPTIM2_IN2/LTDC_R5/~{QUADSPI_BK2_NCS}/~{SAI2_FS_B}passive
U5PB10/DFSDM1/ETH1/I2C2/I2S2/LPTIM2/LTDC/QUADSPI/SPI2/TIM2/USART3passive
U6PG11/ADC1/ADC2/DCMI/DEBUG/ETH1/LTDC/SPDIFRX/UART4/USART1passive
U7PG10/DCMI_D2/DEBUG_TRACED10/~{FMC_NE3}/~{LTDC_B2}/LTDC_G3/~{QUADSPI_BK2_IO2}/~{SAI2_SD_B}/UART8_CTSpassive
U8PD11/ADC1/ADC2/FMC/I2C1/I2C4/LPTIM2/QUADSPI/SAI2/USART3passive
U9VSSpassive
V1PC5/ADC1/ADC2/DFSDM1/ETH1/SAI1/SAI4/SPDIFRXpassive
V2PC4/ADC1_INP4/ADC2_INP4/DFSDM1_CKIN2/ETH1_RXD0/I2S1_MCK/SPDIFRX_IN2passive
V3PB12/DFSDM1/ETH1/FDCAN2/I2C2/I2C6/I2S2/SPI2/TIM1/UART5/USART3passive
V4PB8/DCMI/DFSDM1/ETH1/FDCAN1/HDP/I2C1/I2C4/LTDC/SDMMC1/SDMMC2/TIM16/TIM4/UART4passive
V5PB5/DCMI/ETH1/FDCAN2/I2C1/I2C4/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM17/TIM3/UART5passive
V6PG8/DEBUG/ETH1/LTDC/SAI4/SPDIFRX/SPI6/TIM2/TIM8/USART3/USART6passive
V7PE7/DFSDM1_DATIN2/FMC_D4/FMC_DA4/~{QUADSPI_BK2_IO0}/TIM1_ETR/TIM3_ETR/UART7_RXpassive
V8PF8/DEBUG_TRACED12/~{QUADSPI_BK1_IO0}/~{SAI1_SCK_B}/SPI5_MISO/TIM13_CH1/TIM16_CH1N/UART7_DE/UART7_RTSpassive
V9PF9/DAC1_EXTI9/DEBUG_TRACED13/~{QUADSPI_BK1_IO1}/~{SAI1_FS_B}/SPI5_MOSI/TIM14_CH1/TIM17_CH1N/UART7_CTSpassive
W1VSSpassive
W2PA7/ADC1/ADC2/ETH1/I2S1/QUADSPI/SAI4/SPI1/SPI6/TIM14/TIM1/TIM3/TIM8passive
W3PA6/ADC1/ADC2/DCMI/I2S1/LTDC/SAI4/SPI1/SPI6/TIM13/TIM1/TIM3/TIM8passive
W4PF11/ADC1_EXTI11/ADC1_INP2/ADC2_EXTI11/DCMI_D12/LTDC_G5/~{SAI2_SD_B}/SPI5_MOSIpassive
W5VSSpassive
W7PF7/~{QUADSPI_BK1_IO2}/~{SAI1_MCLK_B}/SPI5_SCK/TIM17_CH1/UART7_TXpassive
W8PG9/DAC1/DCMI/DEBUG/FMC/LTDC/QUADSPI/SAI2/SPDIFRX/USART6passive
1A1PE1/DCMI_D3/~{FMC_NBL1}/I2S2_MCK/LPTIM1_IN2/~{SAI3_SD_B}/UART8_TXpassive
1A2PD10/DFSDM1/FMC/I2C5/I2S3/LTDC/RTC/SAI3/SPI3/TIM16/USART3passive
1A3PE3/DEBUG_TRACED0/FMC_A19/~{SAI1_SD_B}/SDMMC2_CK/~{TIM15_BKIN}passive
1A4PB14/DFSDM1/I2S2/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1/USART3passive
1A5PD2/DCMI_D11/I2C5_SMBA/SDMMC1_CMD/TIM3_ETR/UART4_RX/UART5_RXpassive
1A6VSSpassive
1A7VDD1V2_Unusedpassive
1A8DDR_ZQ/DDR_ZQpassive
1A9DDR_A7/DDR_A7passive
1B1PD6/DCMI/DFSDM1/FMC/I2S3/LTDC/SAI1/SPI3/TIM16/USART2passive
1B2PE14/FMC/LTDC/SAI2/SDMMC1/SPI4/TIM1/UART8passive
1B3VDDCOREpassive
1B4PC12/DCMI/DEBUG/I2S3/RCC/SAI4/SDMMC1/SPI3/UART5/USART3passive
1B5VDDCOREpassive
1B6VDDA1V8_Unusedpassive
1B7VDD1V2_Unusedpassive
1B8VSSpassive
1B9VDDQ_DDRpassive
1C1PD9/DAC1_EXTI9/DCMI_HSYNC/DFSDM1_DATIN3/FMC_D14/FMC_DA14/~{LTDC_B0}/~{SAI3_SD_B}/USART3_RXpassive
1C2PD15/ADC1_EXTI15/ADC2_EXTI15/FMC_D1/FMC_DA1/LTDC_R1/SAI3_MCLK_A/TIM4_CH4/UART8_CTSpassive
1C3VSSpassive
1C4VDDCOREpassive
1C5VSSpassive
1C6VDDCOREpassive
1C7VSSpassive
1C8DDR_DTO1/DDR_DTO1passive
1C9DDR_A5/DDR_A5passive
1D1VBATpassive
1D2VSSpassive
1D3VDDCOREpassive
1D4VSSpassive
1D5VDDCOREpassive
1D6VSSpassive
1D7VDDCOREpassive
1D8DDR_DTO0/DDR_DTO0passive
1D9VDDQ_DDRpassive
1E1PD14/FMC_D0/FMC_DA0/~{SAI3_MCLK_B}/TIM4_CH3/UART8_CTSpassive
1E2VDDpassive
1E3VSSpassive
1E4VDDCOREpassive
1E5VSSpassive
1E6VDDCOREpassive
1E7VSSpassive
1E8VDDCOREpassive
1E9DDR_RASN/DDR_RASNpassive
1F1VDDApassive
1F2VDDApassive
1F3VDDpassive
1F4VSSpassive
1F5VDDCOREpassive
1F6VSSpassive
1F7VDDCOREpassive
1F8DDR_ATO/DDR_ATOpassive
1F9VDDQ_DDRpassive
1G1VSSApassive
1G2VSSpassive
1G3VDDpassive
1G4VDDpassive
1G5VSSpassive
1G6VDDCOREpassive
1G7VSSpassive
1G8VDDCOREpassive
1G9DDR_A6/DDR_A6passive
1H1PA5/ADC1/ADC2/DAC1/I2S1/LTDC/SAI4/SPI1/SPI6/TIM2/TIM8passive
1H2VSSpassive
1H3VSSpassive
1H4VSSpassive
1H5VDDA1V8_REGpassive
1H6VSSpassive
1H7VDD3V3_USBpassive
1H8VSSpassive
1H9VDDQ_DDRpassive
1J1PA4/ADC1/ADC2/DAC1/DCMI/HDP/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM5/USART2passive
1J2PB13/DFSDM1/ETH1/FDCAN2/I2S2/LPTIM2/SPI2/TIM1/UART5/USART3passive
1J3VDDpassive
1J4PE9/DAC1_EXTI9/DFSDM1_CKOUT/FMC_D6/FMC_DA6/~{QUADSPI_BK2_IO2}/TIM1_CH1/UART7_DE/UART7_RTSpassive
1J5VSSpassive
1J6VDDA1V1_REGpassive
1J7PF10/DCMI_D11/LTDC_DE/QUADSPI_CLK/SAI1_D3/SAI1_D4/SAI4_D3/SAI4_D4/~{TIM16_BKIN}passive
1J8USB_RREFpassive
1J9VSSpassive
A10PE4/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15passive
A12DNUpassive
A13DNUpassive
A15JTDO-TRACESWO/DEBUG_JTDO-SWOpassive
A16JTCK-SWCLK/DEBUG_JTCK-SWCLKpassive
A17DDR_DQ0/DDR_DQ0passive
A18DDR_DQ1/DDR_DQ1passive
A19VSSpassive
B10PC10/DCMI/DEBUG/DFSDM1/I2S3/LTDC/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3passive
B11DNUpassive
B12DNUpassive
B13DNUpassive
B14NJTRST/DEBUG_JTRSTpassive
B15JTDI/DEBUG_JTDIpassive
B16DDR_DQ3/DDR_DQ3passive
B17DDR_DQ7/DDR_DQ7passive
B18DDR_DQS0N/DDR_DQS0Npassive
B19DDR_DQS0P/DDR_DQS0Ppassive
C10PC7/DCMI/DFSDM1/HDP/I2S3/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6passive
C11PC11/ADC1/ADC2/DCMI/DEBUG/DFSDM1/I2S3/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3passive
C12DNUpassive
C13VDD_Unusedpassive
C14VSSpassive
C15JTMS-SWDIO/DEBUG_JTMS-SWDIOpassive
C16DDR_RESETN/DDR_RESETNpassive
C17DDR_DQM0/DDR_DQM0passive
C18DDR_DQ2/DDR_DQ2passive
C19DDR_DQ6/DDR_DQ6passive
D17VSSpassive
D18DDR_DQ4/DDR_DQ4passive
D19DDR_DQ5/DDR_DQ5passive
E17DDR_A13/DDR_A13passive
E18DDR_A9/DDR_A9passive
F17DDR_A2/DDR_A2passive
F18VSSpassive
F19DDR_A3/DDR_A3passive
G17VSSpassive
G18DDR_A0/DDR_A0passive
G19~{DDR_BA0}/~{DDR_BA0}passive
H17~{DDR_BA2}/~{DDR_BA2}passive
H18DDR_ODT/DDR_ODTpassive
J17DDR_CSN/DDR_CSNpassive
J18DDR_WEN/DDR_WENpassive
J19DDR_CASN/DDR_CASNpassive
K17VSSpassive
K18DDR_CLKN/DDR_CLKNpassive
K19VSSpassive
L17DDR_CLKP/DDR_CLKPpassive
L18DDR_A15/DDR_A15passive
M17DDR_A10/DDR_A10passive
M18DDR_A12/DDR_A12passive
M19DDR_A1/DDR_A1passive
N17VSSpassive
N18DDR_A14/DDR_A14passive
N19DDR_A11/DDR_A11passive
P17DDR_CKE/DDR_CKEpassive
P18~{DDR_BA1}/~{DDR_BA1}passive
R17DDR_A4/DDR_A4passive
R18DDR_DQ8/DDR_DQ8passive
R19VSSpassive
T17DDR_A8/DDR_A8passive
T18DDR_DQ13/DDR_DQ13passive
T19DDR_DQ10/DDR_DQ10passive
U10PF6/~{QUADSPI_BK1_IO3}/~{SAI1_SD_B}/~{SAI4_SCK_B}/~{SPI5_NSS}/TIM16_CH1/UART7_RXpassive
U11BYPASS_REG1V8passive
U12PE8/DFSDM1_CKIN2/FMC_D5/FMC_DA5/~{QUADSPI_BK2_IO1}/TIM1_CH1N/UART7_TXpassive
U13PD13/FMC_A18/I2C1_SDA/I2C4_SDA/I2S3_MCK/LPTIM1_OUT/~{QUADSPI_BK1_IO3}/SAI2_SCK_A/TIM4_CH2passive
U14PD12/FMC/I2C1/I2C4/LPTIM1/LPTIM2/QUADSPI/SAI2/TIM4/USART3passive
U15PA11/ADC1/ADC2/FDCAN1/I2C5/I2C6/I2S2/LTDC/SPI2/TIM1/UART4/USART1passive
U16PA10/DCMI_D1/I2S3_WS/~{LTDC_B1}/~{SAI4_FS_B}/~{SPI3_NSS}/TIM1_CH3/USART1_RX/USB_OTG_HS_IDpassive
U17DDR_DQ14/DDR_DQ14passive
U18DDR_DQS1N/DDR_DQS1Npassive
U19DDR_DQ9/DDR_DQ9passive
V10USB_DP2/USBH_HS2_DP/USB_OTG_HS_DPpassive
V11PG7/DCMI/DEBUG/LTDC/QUADSPI/SAI1/UART8/USART6passive
V12PE10/DFSDM1_DATIN4/FMC_D7/FMC_DA7/~{QUADSPI_BK2_IO3}/TIM1_CH2N/UART7_CTSpassive
V13PB2/DEBUG/DFSDM1/I2S3/I2S/QUADSPI/SAI1/SPI3/UART4/USART1passive
V14USB_DP1/USBH_HS1_DPpassive
V15PA12/FDCAN1_TX/I2C5_SDA/I2C6_SDA/LTDC_R5/~{SAI2_FS_B}/TIM1_ETR/UART4_TX/USART1_DE/USART1_RTSpassive
V16OTG_VBUS/USB_OTG_HS_VBUSpassive
V17DDR_DQ15/DDR_DQ15passive
V18DDR_DQM1/DDR_DQM1passive
V19DDR_DQS1P/DDR_DQS1Ppassive
W10USB_DM2/USBH_HS2_DM/USB_OTG_HS_DMpassive
W11PB6/CEC/DCMI/DFSDM1/FDCAN2/I2C1/I2C4/QUADSPI/TIM16/TIM4/UART5/USART1passive
W13VSSpassive
W14USB_DM1/USBH_HS1_DMpassive
W16DDR_VREF/DDR_VREFpassive
W17DDR_DQ12/DDR_DQ12passive
W18DDR_DQ11/DDR_DQ11passive
W19VSSpassive

Provenance

Credit
Celestial Altium Library by Issus and contributors (https://github.com/issus/altium-library)
Licence
LicenseRef-Celestial-Altium
Link method
none
Cross-check
not confirmed