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ST MICROELECTRONICS STM32MP153D_2

celestial-altium-MCU_STM32

Symbol

448 pins
Schematic symbol for ST MICROELECTRONICS STM32MP153D_2
Units
12
Kind
part
Grid
on 1.27 mm

Footprint

none
no footprint linked

This symbol carries no usable footprint reference, so nothing is linked. Generating one is a better answer than guessing.

3D model

none
no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

No footprint is linked, so there is nothing to cross-check.

PinNameType
A1VSSpassive
A2PH5/I2C2_SDA/~{SAI4_SD_B}/~{SPI5_NSS}passive
A3PH4/I2C2_SCL/LTDC_G4/LTDC_G5passive
A4PE13/DCMI_D6/DFSDM1_CKIN5/FMC_D10/FMC_DA10/HDP_HDP2/LTDC_DE/~{SAI2_FS_B}/SPI4_MISO/TIM1_CH3passive
A5PK6/DEBUG_TRACED7/HDP_HDP7/~{LTDC_B7}passive
A6PK4/~{LTDC_B5}passive
A7PJ13/~{LTDC_B1}/LTDC_G4passive
A8PD10/DFSDM1/FMC/I2C5/I2S3/LTDC/RTC/SAI3/SPI3/TIM16/USART3passive
A9PD5/~{FMC_NWE}/SDMMC3_D2/USART2_TXpassive
B1PH10/DCMI_D1/I2C1_SMBA/I2C4_SMBA/LTDC_R4/TIM5_CH1passive
B2VSSpassive
B3PH11/ADC1_EXTI11/ADC2_EXTI11/DCMI_D2/I2C1_SCL/I2C4_SCL/LTDC_R5/TIM5_CH2passive
B4PE14/FMC/LTDC/SAI2/SDMMC1/SPI4/TIM1/UART8passive
B5PK7/LTDC_DEpassive
B6PK3/~{LTDC_B4}passive
B7PJ14/~{LTDC_B2}passive
B8PJ12/~{LTDC_B0}/LTDC_G3passive
B9PF1/FMC_A1/I2C2_SCL/SDMMC3_CDIR/SDMMC3_CMDpassive
C1PH15/ADC1_EXTI15/ADC2_EXTI15/DCMI_D11/LTDC_G4/TIM8_CH3Npassive
C2PH14/DCMI_D4/FDCAN1_RX/LTDC_G3/TIM8_CH2N/UART4_RXpassive
C3VSSpassive
C4PE15/ADC1/ADC2/FMC/HDP/LTDC/TIM15/TIM1/UART8/USART2passive
C5PE0/DCMI/FMC/I2S3/LPTIM1/LPTIM2/SAI2/SAI4/SPI3/TIM4/UART8passive
C6PK5/DEBUG_TRACED6/HDP_HDP6/~{LTDC_B6}passive
C7PJ15/ADC1_EXTI15/ADC2_EXTI15/~{LTDC_B3}passive
C8VSSpassive
C9PD4/DFSDM1_CKIN0/~{FMC_NOE}/SAI3_FS_A/SDMMC3_D1/USART2_DE/USART2_RTSpassive
D1PI0/DCMI_D13/I2S2_WS/LTDC_G5/~{SPI2_NSS}/TIM5_CH4passive
D2PI14/DEBUG_TRACECLK/LTDC_CLKpassive
D3PH13/FDCAN1_TX/LTDC_G2/TIM8_CH1N/UART4_TXpassive
D4VSSpassive
D5PE11/ADC1/ADC2/DCMI/DFSDM1/FMC/LTDC/SAI2/SPI4/TIM1/USART6passive
D6PH8/DCMI_HSYNC/I2C3_SDA/LTDC_R2/TIM5_ETRpassive
D7PE1/DCMI_D3/~{FMC_NBL1}/I2S2_MCK/LPTIM1_IN2/~{SAI3_SD_B}/UART8_TXpassive
D8PK0/LTDC_G5/SPI5_SCK/TIM1_CH1N/TIM8_CH3passive
D9PF5/FMC_A5/SDMMC3_D2/USART2_TXpassive
E1PI2/DCMI_D9/I2S2_SDI/LTDC_G7/SPI2_MISO/TIM8_CH4passive
E2PI1/DCMI_D8/I2S2_CK/LTDC_G6/SPI2_SCK/~{TIM8_BKIN2}passive
E3PI3/DCMI_D10/I2S2_SDO/SPI2_MOSI/TIM8_ETRpassive
E4PE12/DFSDM1_DATIN5/FMC_D9/FMC_DA9/~{LTDC_B4}/~{SAI2_SCK_B}/SDMMC1_D0DIR/SPI4_SCK/TIM1_CH3Npassive
E5VSSpassive
E6PH9/DAC1_EXTI9/DCMI_D0/I2C3_SMBA/LTDC_R3/TIM12_CH2passive
E7PK1/DEBUG_TRACED4/HDP_HDP4/LTDC_G6/~{SPI5_NSS}/TIM1_CH1/TIM8_CH3Npassive
E8PK2/DEBUG_TRACED5/HDP_HDP5/LTDC_G7/~{TIM1_BKIN}/~{TIM8_BKIN}passive
E9PE6/DCMI/DEBUG/FMC/LTDC/SAI1/SAI2/SDMMC1/SDMMC2/SPI4/TIM15/TIM1passive
F1PI7/DCMI_D7/~{LTDC_B7}/SAI2_FS_A/TIM8_CH3passive
F2PI5/DCMI_VSYNC/~{LTDC_B5}/SAI2_SCK_A/TIM8_CH1passive
F3PI15/ADC1_EXTI15/ADC2_EXTI15/LTDC_G2/LTDC_R0passive
F4PZ3/I2C2_SDA/I2C4_SDA/I2C5_SDA/I2C6_SDA/I2S1_WS/~{SPI1_NSS}/~{SPI6_NSS}/USART1_CTS/~{USART1_NSS}passive
F5PH12/DCMI_D3/HDP_HDP2/I2C1_SDA/I2C4_SDA/LTDC_R6/TIM5_CH3passive
F6VSSpassive
F7VSSpassive
F8VSSpassive
F9PF4/FMC_A4/SDMMC3_D1/SDMMC3_D123DIR/USART2_RXpassive
G1PZ4/I2C2_SCL/I2C4_SCL/I2C5_SCL/I2C6_SCLpassive
G2PZ0/I2C2_SCL/I2C6_SCL/I2S1_CK/SPI1_SCK/SPI6_SCK/USART1_CKpassive
G3PZ6/I2C2_SCL/I2C4_SMBA/I2C6_SCL/I2S1_MCK/USART1_CK/USART1_RXpassive
G4VSSpassive
G5PI6/DCMI_D6/~{LTDC_B6}/SAI2_SD_A/TIM8_CH2passive
G6VSSpassive
G8VSSpassive
H1PI13/DEBUG_TRACED1/HDP_HDP1/LTDC_VSYNCpassive
H2PI12/DEBUG_TRACED0/HDP_HDP0/LTDC_HSYNCpassive
H3PZ7/I2C2_SDA/I2C6_SDA/USART1_TXpassive
H4PZ5/I2C2_SDA/I2C4_SDA/I2C5_SDA/I2C6_SDA/USART1_DE/USART1_RTSpassive
H5PZ1/I2C2_SDA/I2C4_SDA/I2C5_SDA/I2C6_SDA/I2S1_SDI/SPI1_MISO/SPI6_MISO/USART1_RXpassive
H6PJ8/DEBUG_TRACED14/LTDC_G1/TIM1_CH3N/TIM8_CH1/UART8_TXpassive
H7VSSpassive
H9VDDCOREpassive
J1PJ3/DEBUG_TRACED11/LTDC_R4passive
J2PJ0/DEBUG_TRACED8/LTDC_R1/LTDC_R7passive
J3PJ10/LTDC_G3/SPI5_MOSI/TIM1_CH2N/TIM8_CH2passive
J4PG12/ETH1/FMC/LPTIM1/LTDC/SAI4/SPDIFRX/SPI6/USART6passive
J5PI9/DAC1_EXTI9/FDCAN1_RX/HDP_HDP1/LTDC_VSYNC/UART4_RXpassive
J6PI4/DCMI_D5/~{LTDC_B4}/SAI2_MCLK_A/~{TIM8_BKIN}passive
J8VDDCOREpassive
J9VSSpassive
K1PJ5/DEBUG_TRACED2/HDP_HDP2/LTDC_R6passive
K2PJ4/DEBUG_TRACED12/LTDC_R5passive
K3VSSpassive
K4PJ2/DEBUG_TRACED10/LTDC_R3passive
K5PZ2/I2C2_SCL/I2C4_SMBA/I2C5_SMBA/I2C6_SCL/I2S1_SDO/SPI1_MOSI/SPI6_MOSI/USART1_TXpassive
K6PJ11/ADC1_EXTI11/ADC2_EXTI11/LTDC_G4/SPI5_MISO/TIM1_CH2/TIM8_CH2Npassive
K7VSSpassive
K9VDDCOREpassive
L1PD15/ADC1_EXTI15/ADC2_EXTI15/FMC_D1/FMC_DA1/LTDC_R1/SAI3_MCLK_A/TIM4_CH4/UART8_CTSpassive
L2PJ9/DAC1_EXTI9/DEBUG_TRACED15/LTDC_G2/TIM1_CH3/TIM8_CH1N/UART8_RXpassive
L3PD6/DCMI/DFSDM1/FMC/I2S3/LTDC/SAI1/SPI3/TIM16/USART2passive
L4PJ7/DEBUG_TRACED13/LTDC_G0/TIM8_CH2Npassive
L5PJ6/DEBUG_TRACED3/HDP_HDP3/LTDC_R7/TIM8_CH2passive
L6PJ1/DEBUG_TRACED9/LTDC_R2passive
L8VDDCOREpassive
L9VSSpassive
M1PD8/DFSDM1_CKIN3/FMC_D13/FMC_DA13/~{LTDC_B7}/~{SAI3_SCK_B}/SPDIFRX_IN1/USART3_TXpassive
M2PD9/DAC1_EXTI9/DCMI_HSYNC/DFSDM1_DATIN3/FMC_D14/FMC_DA14/~{LTDC_B0}/~{SAI3_SD_B}/USART3_RXpassive
M3PD14/FMC_D0/FMC_DA0/~{SAI3_MCLK_B}/TIM4_CH3/UART8_CTSpassive
M4VBATpassive
M5VSS_PLLpassive
M6VDD_PLLpassive
M7VSSpassive
M9VDDpassive
N1PI8/PWR_WKUP4/RTC_LSCO/TAMP_IN2/TAMP_OUT3passive
N2PC13/PWR_WKUP3/RTC_LSCO/RTC_TS/TAMP_IN1/TAMP_OUT2/TAMP_OUT3passive
N3BOOT0passive
N4BOOT1passive
N5VDD_ANApassive
N6VREF-passive
N8VDDpassive
N9VSSpassive
P1PC14-OSC32_IN/RCC_OSC32_INpassive
P2PC15-OSC32_OUT/ADC1_EXTI15/ADC2_EXTI15/RCC_OSC32_OUTpassive
P3VSSpassive
P4BOOT2passive
P5VSS_ANApassive
P6VREF+passive
P7VSSpassive
P9VDDpassive
R1NRST_COREpassive
R2NRSTpassive
R3PA14/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_2passive
R4ANA0/ADC1_INN1/ADC1_INP0/ADC2_INN1/ADC2_INP0passive
R5VDDApassive
R6VSSApassive
R8VSSpassive
T1PH0-OSC_IN/RCC_OSC_INpassive
T2PH1-OSC_OUT/RCC_OSC_OUTpassive
T3PI11/ADC1_EXTI11/ADC2_EXTI11/I2S_CKIN/LTDC_G6/PWR_WKUP5/RCC_MCO_1passive
T4PA3/ADC1_INP15/ETH1_COL/LPTIM5_OUT/~{LTDC_B2}/~{LTDC_B5}/PWR_PVD_IN/TIM15_CH2/TIM2_CH4/TIM5_CH4/USART2_RXpassive
T5ANA1/ADC1_INP1/ADC2_INP1passive
T6VSSApassive
T7VSSpassive
T9VSSpassive
U1PWR_LPpassive
U2PDR_ON_COREpassive
U3PC3/ADC1_INN12/ADC1_INP13/DEBUG_TRACECLK/DFSDM1_DATIN1/ETH1_TX_CLK/I2S2_SDO/SPI2_MOSIpassive
U4PG3/DEBUG_TRACED3/DFSDM1_CKIN1/ETH1_TXD7/FMC_A13/~{TIM8_BKIN2}passive
U5PA5/ADC1/ADC2/DAC1/I2S1/LTDC/SAI4/SPI1/SPI6/TIM2/TIM8passive
U6VSSApassive
U7VSSpassive
U8PG5/ETH1_CLK125/FMC_A15/TIM1_ETRpassive
U9VDDpassive
V1PWR_ONpassive
V2PDR_ONpassive
V3PF3/ETH1_TX_ER/FMC_A3passive
V4PA1/ADC1/ETH1/LPTIM3/LTDC/QUADSPI/SAI2/TIM15/TIM2/TIM5/UART4/USART2passive
V5VSSpassive
V6PA4/ADC1/ADC2/DAC1/DCMI/HDP/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM5/USART2passive
V7PF14/ADC2_INN2/ADC2_INP6/DEBUG_TRACED6/DFSDM1_CKIN6/ETH1_RXD6/FMC_A8/I2C1_SCL/I2C4_SCLpassive
V8PF12/ADC1_INN2/ADC1_INP6/DEBUG_TRACED4/ETH1_RXD4/FMC_A6passive
V9PB10/DFSDM1/ETH1/I2C2/I2S2/LPTIM2/LTDC/QUADSPI/SPI2/TIM2/USART3passive
W1PI10/ETH1_RX_ER/HDP_HDP0/LTDC_HSYNC/USART3_CTS/~{USART3_NSS}passive
W2PH7/DCMI_D9/ETH1_RXD3/I2C3_SCL/SPI5_MISOpassive
W3PA13/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_1/UART4_TXpassive
W4PG2/DEBUG_TRACED2/ETH1_TXD6/FMC_A12/RCC_MCO_2/~{TIM8_BKIN}passive
W5PG0/DEBUG_TRACED0/DFSDM1_DATIN0/ETH1_TXD4/FMC_A10passive
W6PF15/ADC1_EXTI15/ADC2_EXTI15/DEBUG_TRACED7/ETH1_RXD7/FMC_A9/I2C1_SDA/I2C4_SDApassive
W7PF13/ADC2_INP2/DEBUG_TRACED5/DFSDM1_DATIN3/DFSDM1_DATIN6/ETH1_RXD5/FMC_A7/I2C1_SMBA/I2C4_SMBApassive
W8PF11/ADC1_EXTI11/ADC1_INP2/ADC2_EXTI11/DCMI_D12/LTDC_G5/~{SAI2_SD_B}/SPI5_MOSIpassive
W9PA6/ADC1/ADC2/DCMI/I2S1/LTDC/SAI4/SPI1/SPI6/TIM13/TIM1/TIM3/TIM8passive
Y1PC2/ADC1_INN11/ADC1_INP12/DCMI_PIXCLK/DFSDM1_CKIN1/DFSDM1_CKOUT/ETH1_TXD2/I2S2_SDI/SPI2_MISOpassive
Y2PE2/DEBUG_TRACECLK/ETH1_TXD3/FMC_A23/I2C4_SCL/~{QUADSPI_BK1_IO2}/SAI1_CK1/SAI1_MCLK_A/SPI4_SCKpassive
Y3VSSpassive
Y4PG1/DEBUG_TRACED1/ETH1_TXD5/FMC_A11passive
Y5PB11/ADC1/ADC2/DFSDM1/ETH1/I2C2/LPTIM2/LTDC/TIM2/USART3passive
Y6PH3/DFSDM1_CKIN4/ETH1_COL/LTDC_R1/~{QUADSPI_BK2_IO1}/~{SAI2_MCLK_B}passive
Y7VSSpassive
Y8PG8/DEBUG/ETH1/LTDC/SAI4/SPDIFRX/SPI6/TIM2/TIM8/USART3/USART6passive
Y9PA7/ADC1/ADC2/ETH1/I2S1/QUADSPI/SAI4/SPI1/SPI6/TIM14/TIM1/TIM3/TIM8passive
A10PE3/DEBUG_TRACED0/FMC_A19/~{SAI1_SD_B}/SDMMC2_CK/~{TIM15_BKIN}passive
A11PA9/DAC1_EXTI9/DCMI_D0/I2C3_SMBA/I2S2_CK/LTDC_R5/SDMMC2_CDIR/SDMMC2_D5/SPI2_SCK/TIM1_CH2/USART1_TXpassive
A12PB3/DEBUG/I2S1/I2S3/SAI4/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART7passive
A13PB14/DFSDM1/I2S2/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1/USART3passive
A14VDD_Unusedpassive
A15DNUpassive
A16DNUpassive
A17DNUpassive
A18VDD1V2_Unusedpassive
A19VSSpassive
A20DDR_DQ20/DDR_DQ20passive
A21DDR_DQ23/DDR_DQ23passive
A22VSSpassive
AA1PG13/DEBUG/ETH1/FMC/LPTIM1/LTDC/SAI1/SAI4/SPI6/USART6passive
AA2PG14/DEBUG/ETH1/FMC/LPTIM1/LTDC/QUADSPI/SAI4/SPI6/USART6passive
AA3PA0/ADC1/ETH1/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/TIM8/UART4/USART2passive
AA4VSSpassive
AA5PB1/ADC1_INP5/ADC2_INP5/DFSDM1_DATIN1/ETH1_RXD3/LTDC_G0/LTDC_R6/TIM1_CH3N/TIM3_CH4/TIM8_CH3Npassive
AA6PC5/ADC1/ADC2/DFSDM1/ETH1/SAI1/SAI4/SPDIFRXpassive
AA7PB12/DFSDM1/ETH1/FDCAN2/I2C2/I2C6/I2S2/SPI2/TIM1/UART5/USART3passive
AA8PB5/DCMI/ETH1/FDCAN2/I2C1/I2C4/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM17/TIM3/UART5passive
AA9PG10/DCMI_D2/DEBUG_TRACED10/~{FMC_NE3}/~{LTDC_B2}/LTDC_G3/~{QUADSPI_BK2_IO2}/~{SAI2_SD_B}/UART8_CTSpassive
AB1VSSpassive
AB2PA2/ADC1/ETH1/LPTIM4/LTDC/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/USART2passive
AB3PC1/ADC1/ADC2/DEBUG/DFSDM1/ETH1/I2S2/PWR/SAI1/SDMMC2/SPI2/TAMPpassive
AB4PG4/ETH1_GTX_CLK/FMC_A14/~{TIM1_BKIN2}passive
AB5PB0/ADC1/ADC2/DFSDM1/ETH1/LTDC/TIM1/TIM3/TIM8/UART4passive
AB6PC4/ADC1_INP4/ADC2_INP4/DFSDM1_CKIN2/ETH1_RXD0/I2S1_MCK/SPDIFRX_IN2passive
AB7PH2/ETH1_CRS/LPTIM1_IN2/LTDC_R0/~{QUADSPI_BK2_IO0}/~{SAI2_SCK_B}passive
AB8PB8/DCMI/DFSDM1/ETH1/FDCAN1/HDP/I2C1/I2C4/LTDC/SDMMC1/SDMMC2/TIM16/TIM4/UART4passive
AB9PD11/ADC1/ADC2/FMC/I2C1/I2C4/LPTIM2/QUADSPI/SAI2/USART3passive
B10PD1/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4passive
B11PD3/DCMI/DFSDM1/FMC/HDP/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/USART2passive
B12PB15/ADC1/ADC2/DFSDM1/I2S2/RTC/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1passive
B13PA8/I2C3/I2S3/LTDC/RCC/SAI4/SDMMC2/SPI3/TIM1/TIM8/UART7/USART1/USBpassive
B14VDDA1V8_Unusedpassive
B15DNUpassive
B16DNUpassive
B17DNUpassive
B18VDD1V2_Unusedpassive
B19VSSpassive
B20DDR_DQ19/DDR_DQ19passive
B21DDR_DQ16/DDR_DQ16passive
B22DDR_DQS2N/DDR_DQS2Npassive
C10PD0/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4passive
C11VSSpassive
C12PE5/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15passive
C13PB4/DEBUG/I2S1/I2S2/I2S3/SAI4/SDMMC2/SPI1/SPI2/SPI3/SPI6/TIM16/TIM3/UART7passive
C14VSSpassive
C15VSSpassive
C16VSSpassive
C17VSSpassive
C18VSSpassive
C19VSSpassive
C20VSSpassive
C21DDR_DQS2P/DDR_DQS2Ppassive
C22DDR_DQM2/DDR_DQM2passive
D10PG15/ADC1/ADC2/DCMI/DEBUG/I2C2/SAI1/SDMMC3/USART6passive
D11PG6/DCMI_D12/DEBUG_TRACED14/LTDC_R7/SDMMC2_CMD/~{TIM17_BKIN}passive
D12PD2/DCMI_D11/I2C5_SMBA/SDMMC1_CMD/TIM3_ETR/UART4_RX/UART5_RXpassive
D13PC7/DCMI/DFSDM1/HDP/I2S3/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6passive
D14PC9/DAC1/DCMI/DEBUG/I2C3/I2S/LTDC/QUADSPI/SDMMC1/TIM3/TIM8/UART5passive
D15PC11/ADC1/ADC2/DCMI/DEBUG/DFSDM1/I2S3/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3passive
D16JTDI/DEBUG_JTDIpassive
D17JTCK-SWCLK/DEBUG_JTCK-SWCLKpassive
D18VDD_PLL2passive
D19VSS_PLL2passive
D20DDR_DQ22/DDR_DQ22passive
D21DDR_DQ17/DDR_DQ17passive
D22DDR_DQ18/DDR_DQ18passive
E10PF0/FMC_A0/I2C2_SDA/SDMMC3_CKIN/SDMMC3_D0passive
E11PA15/CEC/ADC1/ADC2/DEBUG/I2S1/I2S3/LTDC/SAI4/SDMMC1/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART4/UART7passive
E12PC12/DCMI/DEBUG/I2S3/RCC/SAI4/SDMMC1/SPI3/UART5/USART3passive
E13PC6/DCMI/DFSDM1/HDP/I2S2/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6passive
E14PC8/DCMI_D2/DEBUG_TRACED0/SDMMC1_D0/TIM3_CH3/TIM8_CH3/UART4_TX/UART5_DE/UART5_RTS/USART6_CKpassive
E15NJTRST/DEBUG_JTRSTpassive
E16JTDO-TRACESWO/DEBUG_JTDO-SWOpassive
E17JTMS-SWDIO/DEBUG_JTMS-SWDIOpassive
E18VDDQ_DDRpassive
E19VSSpassive
E20DDR_DQ3/DDR_DQ3passive
E21DDR_DQ0/DDR_DQ0passive
E22DDR_DQ21/DDR_DQ21passive
F10PD7/DEBUG_TRACED6/DFSDM1_CKIN1/DFSDM1_DATIN4/~{FMC_NE1}/I2C2_SCL/SDMMC3_D3/SPDIFRX_IN0/USART2_CKpassive
F11PB7/DCMI_VSYNC/DFSDM1_CKIN5/~{FMC_NL}/I2C1_SDA/I2C4_SDA/SDMMC2_D1/TIM17_CH1N/TIM4_CH2/USART1_RXpassive
F12PB9/DAC1/DCMI/DFSDM1/FDCAN1/HDP/I2C1/I2C4/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/TIM17/TIM4/UART4passive
F13PF2/FMC_A2/I2C2_SMBA/SDMMC1_D0DIR/SDMMC2_D0DIR/SDMMC3_D0DIRpassive
F14PC10/DCMI/DEBUG/DFSDM1/I2S3/LTDC/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3passive
F15PE4/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15passive
F16VSSpassive
F17VDDQ_DDRpassive
F18DDR_A7/DDR_A7passive
F19DDR_RESETN/DDR_RESETNpassive
F20VSSpassive
F21DDR_DQ1/DDR_DQ1passive
G10VSSpassive
G12VSSpassive
G14VSSpassive
G16VDDQ_DDRpassive
G17VSSpassive
G18DDR_A13/DDR_A13passive
G19DDR_DQ7/DDR_DQ7passive
G20DDR_DQM0/DDR_DQM0passive
G21DDR_DQS0N/DDR_DQS0Npassive
G22DDR_DQS0P/DDR_DQS0Ppassive
H11VDDCOREpassive
H13VDDCOREpassive
H15VDDCOREpassive
H17VDDQ_DDRpassive
H18DDR_A9/DDR_A9passive
H19DDR_A5/DDR_A5passive
H20DDR_DQ5/DDR_DQ5passive
H21DDR_DQ2/DDR_DQ2passive
H22DDR_DQ6/DDR_DQ6passive
J10VDDCOREpassive
J11VSSpassive
J12VDDCOREpassive
J13VSSpassive
J14VDDCOREpassive
J16VDDQ_DDRpassive
J17VSSpassive
J18DDR_A2/DDR_A2passive
J19DDR_A3/DDR_A3passive
J20VSSpassive
J21DDR_DQ4/DDR_DQ4passive
K10VSSpassive
K11VDDCOREpassive
K12VSSpassive
K13VDDCOREpassive
K14VSSpassive
K15VDDCOREpassive
K17VDDQ_DDRpassive
K18~{DDR_BA2}/~{DDR_BA2}passive
K19DDR_A0/DDR_A0passive
K20~{DDR_BA0}/~{DDR_BA0}passive
K21DDR_DTO1/DDR_DTO1passive
K22DDR_ZQ/DDR_ZQpassive
L10VDDCOREpassive
L11VSSpassive
L12VDDCOREpassive
L13VSSpassive
L14VDDCOREpassive
L16VDDQ_DDRpassive
L17VSSpassive
L18DDR_CSN/DDR_CSNpassive
L19VSSpassive
L20VSSpassive
L21DDR_ODT/DDR_ODTpassive
L22DDR_DTO0/DDR_DTO0passive
M10VSSpassive
M11VDDCOREpassive
M12VSSpassive
M13VDDCOREpassive
M14VSSpassive
M15VDDCOREpassive
M17VDDQ_DDRpassive
M18DDR_A1/DDR_A1passive
M19DDR_A15/DDR_A15passive
M20DDR_RASN/DDR_RASNpassive
M21DDR_WEN/DDR_WENpassive
M22DDR_CASN/DDR_CASNpassive
N10VDDpassive
N11VSSpassive
N12VDDCOREpassive
N13VSSpassive
N14VDDCOREpassive
N16VDDQ_DDRpassive
N17VSSpassive
N18DDR_A10/DDR_A10passive
N19DDR_A12/DDR_A12passive
N20DDR_CLKP/DDR_CLKPpassive
N21DDR_CLKN/DDR_CLKNpassive
N22DDR_DQ8/DDR_DQ8passive
P10VSSpassive
P11VDDpassive
P12VSSpassive
P13VDDCOREpassive
P14VSSpassive
P15VDDCOREpassive
P17VDDQ_DDRpassive
P18DDR_A14/DDR_A14passive
P19DDR_A11/DDR_A11passive
P20VSSpassive
P21DDR_DQ10/DDR_DQ10passive
R10VDDpassive
R12VDDpassive
R14VDDCOREpassive
R16VDDQ_DDRpassive
R17VSSpassive
R18~{DDR_BA1}/~{DDR_BA1}passive
R19DDR_CKE/DDR_CKEpassive
R20DDR_DQ13/DDR_DQ13passive
R21DDR_DQ9/DDR_DQ9passive
R22DDR_DQS1N/DDR_DQS1Npassive
T11VSSpassive
T13VDDpassive
T15VDDCOREpassive
T17VDDQ_DDRpassive
T18DDR_A4/DDR_A4passive
T19VSSpassive
T20DDR_DQ11/DDR_DQ11passive
T21DDR_DQM1/DDR_DQM1passive
T22DDR_DQS1P/DDR_DQS1Ppassive
U10PC0/ADC1_INP10/ADC2_INP10/DFSDM1_CKIN0/DFSDM1_DATIN4/LPTIM2_IN2/LTDC_R5/~{QUADSPI_BK2_NCS}/~{SAI2_FS_B}passive
U11PG11/ADC1/ADC2/DCMI/DEBUG/ETH1/LTDC/SPDIFRX/UART4/USART1passive
U12VDDpassive
U13VSSpassive
U14VDDpassive
U15VSSpassive
U16VDDQ_DDRpassive
U17VSSpassive
U18DDR_A8/DDR_A8passive
U19DDR_A6/DDR_A6passive
U20VSSpassive
U21DDR_DQ14/DDR_DQ14passive
V10PB13/DFSDM1/ETH1/FDCAN2/I2S2/LPTIM2/SPI2/TIM1/UART5/USART3passive
V11PH6/DCMI_D8/ETH1_RXD2/I2C2_SMBA/SPI5_SCK/TIM12_CH1passive
V12PF10/DCMI_D11/LTDC_DE/QUADSPI_CLK/SAI1_D3/SAI1_D4/SAI4_D3/SAI4_D4/~{TIM16_BKIN}passive
V13PB2/DEBUG/DFSDM1/I2S3/I2S/QUADSPI/SAI1/SPI3/UART4/USART1passive
V14PD13/FMC_A18/I2C1_SDA/I2C4_SDA/I2S3_MCK/LPTIM1_OUT/~{QUADSPI_BK1_IO3}/SAI2_SCK_A/TIM4_CH2passive
V15OTG_VBUS/USB_OTG_HS_VBUSpassive
V16VSSpassive
V17VDDQ_DDRpassive
V18VSSpassive
V19VSSpassive
V20DDR_DQ12/DDR_DQ12passive
V21DDR_DQ15/DDR_DQ15passive
V22DDR_DQ24/DDR_DQ24passive
W10PE7/DFSDM1_DATIN2/FMC_D4/FMC_DA4/~{QUADSPI_BK2_IO0}/TIM1_ETR/TIM3_ETR/UART7_RXpassive
W11PE9/DAC1_EXTI9/DFSDM1_CKOUT/FMC_D6/FMC_DA6/~{QUADSPI_BK2_IO2}/TIM1_CH1/UART7_DE/UART7_RTSpassive
W12PD12/FMC/I2C1/I2C4/LPTIM1/LPTIM2/QUADSPI/SAI2/TIM4/USART3passive
W13PB6/CEC/DCMI/DFSDM1/FDCAN2/I2C1/I2C4/QUADSPI/TIM16/TIM4/UART5/USART1passive
W14PE10/DFSDM1_DATIN4/FMC_D7/FMC_DA7/~{QUADSPI_BK2_IO3}/TIM1_CH2N/UART7_CTSpassive
W15PG9/DAC1/DCMI/DEBUG/FMC/LTDC/QUADSPI/SAI2/SPDIFRX/USART6passive
W16PA12/FDCAN1_TX/I2C5_SDA/I2C6_SDA/LTDC_R5/~{SAI2_FS_B}/TIM1_ETR/UART4_TX/USART1_DE/USART1_RTSpassive
W17VSSpassive
W18VDDQ_DDRpassive
W19VSSpassive
W20DDR_DQ25/DDR_DQ25passive
W21DDR_DQ31/DDR_DQ31passive
W22DDR_DQ30/DDR_DQ30passive
Y10VSSpassive
Y11PG7/DCMI/DEBUG/LTDC/QUADSPI/SAI1/UART8/USART6passive
Y12PE8/DFSDM1_CKIN2/FMC_D5/FMC_DA5/~{QUADSPI_BK2_IO1}/TIM1_CH1N/UART7_TXpassive
Y13VSS_USBHSpassive
Y14VSS_USBHSpassive
Y15VSS_USBHSpassive
Y16PA11/ADC1/ADC2/FDCAN1/I2C5/I2C6/I2S2/LTDC/SPI2/TIM1/UART4/USART1passive
Y17PA10/DCMI_D1/I2S3_WS/~{LTDC_B1}/~{SAI4_FS_B}/~{SPI3_NSS}/TIM1_CH3/USART1_RX/USB_OTG_HS_IDpassive
Y18VSSpassive
Y19VDDQ_DDRpassive
Y20VSSpassive
Y21DDR_DQS3P/DDR_DQS3Ppassive
Y22DDR_DQS3N/DDR_DQS3Npassive
AA10PF7/~{QUADSPI_BK1_IO2}/~{SAI1_MCLK_B}/SPI5_SCK/TIM17_CH1/UART7_TXpassive
AA11PF6/~{QUADSPI_BK1_IO3}/~{SAI1_SD_B}/~{SAI4_SCK_B}/~{SPI5_NSS}/TIM16_CH1/UART7_RXpassive
AA12BYPASS_REG1V8passive
AA13VSS_USBHSpassive
AA14USB_DM2/USBH_HS2_DM/USB_OTG_HS_DMpassive
AA15USB_DP1/USBH_HS1_DPpassive
AA16VSS_USBHSpassive
AA17USB_RREFpassive
AA18VSSpassive
AA19DDR_ATO/DDR_ATOpassive
AA20DDR_DQ29/DDR_DQ29passive
AA21DDR_DQ28/DDR_DQ28passive
AA22DDR_DQM3/DDR_DQM3passive
AB10PF8/DEBUG_TRACED12/~{QUADSPI_BK1_IO0}/~{SAI1_SCK_B}/SPI5_MISO/TIM13_CH1/TIM16_CH1N/UART7_DE/UART7_RTSpassive
AB11PF9/DAC1_EXTI9/DEBUG_TRACED13/~{QUADSPI_BK1_IO1}/~{SAI1_FS_B}/SPI5_MOSI/TIM14_CH1/TIM17_CH1N/UART7_CTSpassive
AB12VDDA1V8_REGpassive
AB13VDD3V3_USBHSpassive
AB14USB_DP2/USBH_HS2_DP/USB_OTG_HS_DPpassive
AB15USB_DM1/USBH_HS1_DMpassive
AB16VDD3V3_USBFSpassive
AB17VDDA1V1_REGpassive
AB18VSSpassive
AB19DDR_VREF/DDR_VREFpassive
AB20DDR_DQ27/DDR_DQ27passive
AB21DDR_DQ26/DDR_DQ26passive
AB22VSSpassive

Provenance

Credit
Celestial Altium Library by Issus and contributors (https://github.com/issus/altium-library)
Licence
LicenseRef-Celestial-Altium
Link method
none
Cross-check
not confirmed