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ST MICROELECTRONICS STM32MP157A_2

celestial-altium-MCU_STM32

Symbol

354 pins
Schematic symbol for ST MICROELECTRONICS STM32MP157A_2
Units
8
Kind
part
Grid
on 1.27 mm

Footprint

none
no footprint linked

This symbol carries no usable footprint reference, so nothing is linked. Generating one is a better answer than guessing.

3D model

none
no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

No footprint is linked, so there is nothing to cross-check.

PinNameType
A1VSSpassive
A2PG15/ADC1/ADC2/DCMI/DEBUG/I2C2/SAI1/SDMMC3/USART6passive
A3PD0/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4passive
A4PD1/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4passive
A5PE3/DEBUG_TRACED0/FMC_A19/~{SAI1_SD_B}/SDMMC2_CK/~{TIM15_BKIN}passive
A6PG6/DCMI_D12/DEBUG_TRACED14/LTDC_R7/SDMMC2_CMD/~{TIM17_BKIN}passive
A7PB3/DEBUG/I2S1/I2S3/SAI4/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART7passive
A8PB15/ADC1/ADC2/DFSDM1/I2S2/RTC/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1passive
A9PC7/DCMI/DFSDM1/HDP/I2S3/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6passive
B1PE1/DCMI_D3/~{FMC_NBL1}/I2S2_MCK/LPTIM1_IN2/~{SAI3_SD_B}/UART8_TXpassive
B2VSSpassive
B3PE6/DCMI/DEBUG/FMC/LTDC/SAI1/SAI2/SDMMC1/SDMMC2/SPI4/TIM15/TIM1passive
B4PD7/DEBUG_TRACED6/DFSDM1_CKIN1/DFSDM1_DATIN4/~{FMC_NE1}/I2C2_SCL/SDMMC3_D3/SPDIFRX_IN0/USART2_CKpassive
B5PB7/DCMI_VSYNC/DFSDM1_CKIN5/~{FMC_NL}/I2C1_SDA/I2C4_SDA/SDMMC2_D1/TIM17_CH1N/TIM4_CH2/USART1_RXpassive
B6VSSpassive
B7PE5/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15passive
B8PA8/I2C3/I2S3/LTDC/RCC/SAI4/SDMMC2/SPI3/TIM1/TIM8/UART7/USART1/USBpassive
B9PB4/DEBUG/I2S1/I2S2/I2S3/SAI4/SDMMC2/SPI1/SPI2/SPI3/SPI6/TIM16/TIM3/UART7passive
C1PE11/ADC1/ADC2/DCMI/DFSDM1/FMC/LTDC/SAI2/SPI4/TIM1/USART6passive
C2PE13/DCMI_D6/DFSDM1_CKIN5/FMC_D10/FMC_DA10/HDP_HDP2/LTDC_DE/~{SAI2_FS_B}/SPI4_MISO/TIM1_CH3passive
C3VSSpassive
C4PE0/DCMI/FMC/I2S3/LPTIM1/LPTIM2/SAI2/SAI4/SPI3/TIM4/UART8passive
C5PD10/DFSDM1/FMC/I2C5/I2S3/LTDC/RTC/SAI3/SPI3/TIM16/USART3passive
C6PD3/DCMI/DFSDM1/FMC/HDP/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/USART2passive
C7PA15/CEC/ADC1/ADC2/DEBUG/I2S1/I2S3/LTDC/SAI4/SDMMC1/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART4/UART7passive
C8PA9/DAC1_EXTI9/DCMI_D0/I2C3_SMBA/I2S2_CK/LTDC_R5/SDMMC2_CDIR/SDMMC2_D5/SPI2_SCK/TIM1_CH2/USART1_TXpassive
C9PB14/DFSDM1/I2S2/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1/USART3passive
D1VSSpassive
D2PE12/DFSDM1_DATIN5/FMC_D9/FMC_DA9/~{LTDC_B4}/~{SAI2_SCK_B}/SDMMC1_D0DIR/SPI4_SCK/TIM1_CH3Npassive
D3PE14/FMC/LTDC/SAI2/SDMMC1/SPI4/TIM1/UART8passive
D4VSSpassive
D5VSSpassive
D6PD4/DFSDM1_CKIN0/~{FMC_NOE}/SAI3_FS_A/SDMMC3_D1/USART2_DE/USART2_RTSpassive
D7PD5/~{FMC_NWE}/SDMMC3_D2/USART2_TXpassive
D8VSSpassive
D9PB9/DAC1/DCMI/DFSDM1/FDCAN1/HDP/I2C1/I2C4/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/TIM17/TIM4/UART4passive
E1PE15/ADC1/ADC2/FMC/HDP/LTDC/TIM15/TIM1/UART8/USART2passive
E2VSSpassive
E3PD6/DCMI/DFSDM1/FMC/I2S3/LTDC/SAI1/SPI3/TIM16/USART2passive
E4VSSpassive
E5VSSpassive
E6VSSpassive
E7VDDCOREpassive
E8VSSpassive
E9VDDCOREpassive
F1PG12/ETH1/FMC/LPTIM1/LTDC/SAI4/SPDIFRX/SPI6/USART6passive
F2PD8/DFSDM1_CKIN3/FMC_D13/FMC_DA13/~{LTDC_B7}/~{SAI3_SCK_B}/SPDIFRX_IN1/USART3_TXpassive
F3PD14/FMC_D0/FMC_DA0/~{SAI3_MCLK_B}/TIM4_CH3/UART8_CTSpassive
F4VDDCOREpassive
F5VSSpassive
F6VDDCOREpassive
F7VSSpassive
F8VDDCOREpassive
F9VSSpassive
G1PD15/ADC1_EXTI15/ADC2_EXTI15/FMC_D1/FMC_DA1/LTDC_R1/SAI3_MCLK_A/TIM4_CH4/UART8_CTSpassive
G2VSSpassive
G3PD9/DAC1_EXTI9/DCMI_HSYNC/DFSDM1_DATIN3/FMC_D14/FMC_DA14/~{LTDC_B0}/~{SAI3_SD_B}/USART3_RXpassive
G4VSSpassive
G5VDDCOREpassive
G6VSSpassive
G7VDDCOREpassive
G8VSSpassive
G9VDDCOREpassive
H1PC14-OSC32_IN/RCC_OSC32_INpassive
H2PC15-OSC32_OUT/ADC1_EXTI15/ADC2_EXTI15/RCC_OSC32_OUTpassive
H3VBATpassive
H4VDDCOREpassive
H5VSSpassive
H6VDDCOREpassive
H7VSSpassive
H8VDDCOREpassive
H9VSSpassive
J1NRSTpassive
J2NRST_COREpassive
J3VSSpassive
J4VSS_PLLpassive
J5VDD_PLLpassive
J6VSSpassive
J7VDDCOREpassive
J8VSSpassive
J9VDDCOREpassive
K1BOOT0passive
K2VSSpassive
K3PC13/PWR_WKUP3/RTC_LSCO/RTC_TS/TAMP_IN1/TAMP_OUT2/TAMP_OUT3passive
K4BOOT1passive
K5VSSpassive
K6VDDpassive
K7VSSpassive
K8VDDCOREpassive
K9VSSpassive
L1PWR_ONpassive
L2BOOT2passive
L3VDD_ANApassive
L4VSS_ANApassive
L5VDDpassive
L6VSSpassive
L7VDDpassive
L8VSSpassive
L9VDDCOREpassive
M1PH0-OSC_IN/RCC_OSC_INpassive
M2PH1-OSC_OUT/RCC_OSC_OUTpassive
M3VREF-passive
M4VDDApassive
M5VSSpassive
M6VDDpassive
M7VSSpassive
M8VDDpassive
M9VSSpassive
N1PDR_ON_COREpassive
N2PDR_ONpassive
N3VREF+passive
N4VSSApassive
N5VDDpassive
N6VSSpassive
N7VDDpassive
N8VSSpassive
N9VDDpassive
P1PWR_LPpassive
P2PA13/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_1/UART4_TXpassive
P3PA3/ADC1_INP15/ETH1_COL/LPTIM5_OUT/~{LTDC_B2}/~{LTDC_B5}/PWR_PVD_IN/TIM15_CH2/TIM2_CH4/TIM5_CH4/USART2_RXpassive
P4PA5/ADC1/ADC2/DAC1/I2S1/LTDC/SAI4/SPI1/SPI6/TIM2/TIM8passive
P5VSSApassive
P6VDDpassive
P7VSSpassive
P8VDDpassive
P9VSSpassive
R1PA14/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_2passive
R2VSSpassive
R3PA0/ADC1/ETH1/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/TIM8/UART4/USART2passive
R4PA4/ADC1/ADC2/DAC1/DCMI/HDP/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM5/USART2passive
R5VSSApassive
R6VSSpassive
R7VDDpassive
R8VSSpassive
R9VDDpassive
T1PE2/DEBUG_TRACECLK/ETH1_TXD3/FMC_A23/I2C4_SCL/~{QUADSPI_BK1_IO2}/SAI1_CK1/SAI1_MCLK_A/SPI4_SCKpassive
T2PC2/ADC1_INN11/ADC1_INP12/DCMI_PIXCLK/DFSDM1_CKIN1/DFSDM1_CKOUT/ETH1_TXD2/I2S2_SDI/SPI2_MISOpassive
T3PC3/ADC1_INN12/ADC1_INP13/DEBUG_TRACECLK/DFSDM1_DATIN1/ETH1_TX_CLK/I2S2_SDO/SPI2_MOSIpassive
T4VSSpassive
T5PA6/ADC1/ADC2/DCMI/I2S1/LTDC/SAI4/SPI1/SPI6/TIM13/TIM1/TIM3/TIM8passive
T6PA7/ADC1/ADC2/ETH1/I2S1/QUADSPI/SAI4/SPI1/SPI6/TIM14/TIM1/TIM3/TIM8passive
T7PC0/ADC1_INP10/ADC2_INP10/DFSDM1_CKIN0/DFSDM1_DATIN4/LPTIM2_IN2/LTDC_R5/~{QUADSPI_BK2_NCS}/~{SAI2_FS_B}passive
T8PB5/DCMI/ETH1/FDCAN2/I2C1/I2C4/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM17/TIM3/UART5passive
T9PB13/DFSDM1/ETH1/FDCAN2/I2S2/LPTIM2/SPI2/TIM1/UART5/USART3passive
U1PG14/DEBUG/ETH1/FMC/LPTIM1/LTDC/QUADSPI/SAI4/SPI6/USART6passive
U2PG13/DEBUG/ETH1/FMC/LPTIM1/LTDC/SAI1/SAI4/SPI6/USART6passive
U3VSSpassive
U4PA1/ADC1/ETH1/LPTIM3/LTDC/QUADSPI/SAI2/TIM15/TIM2/TIM5/UART4/USART2passive
U5PF11/ADC1_EXTI11/ADC1_INP2/ADC2_EXTI11/DCMI_D12/LTDC_G5/~{SAI2_SD_B}/SPI5_MOSIpassive
U6VSSpassive
U7PG8/DEBUG/ETH1/LTDC/SAI4/SPDIFRX/SPI6/TIM2/TIM8/USART3/USART6passive
U8VSSpassive
U9PF10/DCMI_D11/LTDC_DE/QUADSPI_CLK/SAI1_D3/SAI1_D4/SAI4_D3/SAI4_D4/~{TIM16_BKIN}passive
V1PB11/ADC1/ADC2/DFSDM1/DSIHOST/ETH1/I2C2/LPTIM2/LTDC/TIM2/USART3passive
V2PC1/ADC1/ADC2/DEBUG/DFSDM1/ETH1/I2S2/PWR/SAI1/SDMMC2/SPI2/TAMPpassive
V3PB1/ADC1_INP5/ADC2_INP5/DFSDM1_DATIN1/ETH1_RXD3/LTDC_G0/LTDC_R6/TIM1_CH3N/TIM3_CH4/TIM8_CH3Npassive
V4PC5/ADC1/ADC2/DFSDM1/ETH1/SAI1/SAI4/SPDIFRXpassive
V5PB12/DFSDM1/ETH1/FDCAN2/I2C2/I2C6/I2S2/SPI2/TIM1/UART5/USART3passive
V6PG11/ADC1/ADC2/DCMI/DEBUG/ETH1/LTDC/SPDIFRX/UART4/USART1passive
V7PG10/DCMI_D2/DEBUG_TRACED10/~{FMC_NE3}/~{LTDC_B2}/LTDC_G3/~{QUADSPI_BK2_IO2}/~{SAI2_SD_B}/UART8_CTSpassive
V8PD11/ADC1/ADC2/FMC/I2C1/I2C4/LPTIM2/QUADSPI/SAI2/USART3passive
V9PF6/~{QUADSPI_BK1_IO3}/~{SAI1_SD_B}/~{SAI4_SCK_B}/~{SPI5_NSS}/TIM16_CH1/UART7_RXpassive
W1VSSpassive
W2PA2/ADC1/ETH1/LPTIM4/LTDC/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/USART2passive
W3PB0/ADC1/ADC2/DFSDM1/ETH1/LTDC/TIM1/TIM3/TIM8/UART4passive
W4PC4/ADC1_INP4/ADC2_INP4/DFSDM1_CKIN2/ETH1_RXD0/I2S1_MCK/SPDIFRX_IN2passive
W5PB10/DFSDM1/ETH1/I2C2/I2S2/LPTIM2/LTDC/QUADSPI/SPI2/TIM2/USART3passive
W6PB8/DCMI/DFSDM1/ETH1/FDCAN1/HDP/I2C1/I2C4/LTDC/SDMMC1/SDMMC2/TIM16/TIM4/UART4passive
W7PE9/DAC1_EXTI9/DFSDM1_CKOUT/FMC_D6/FMC_DA6/~{QUADSPI_BK2_IO2}/TIM1_CH1/UART7_DE/UART7_RTSpassive
W8PF7/~{QUADSPI_BK1_IO2}/~{SAI1_MCLK_B}/SPI5_SCK/TIM17_CH1/UART7_TXpassive
W9PF9/DAC1_EXTI9/DEBUG_TRACED13/~{QUADSPI_BK1_IO1}/~{SAI1_FS_B}/SPI5_MOSI/TIM14_CH1/TIM17_CH1N/UART7_CTSpassive
A10PC9/DAC1/DCMI/DEBUG/I2C3/I2S/LTDC/QUADSPI/SDMMC1/TIM3/TIM8/UART5passive
A11PC11/ADC1/ADC2/DCMI/DEBUG/DFSDM1/I2S3/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3passive
A12VDD_DSIpassive
A13DSIHOST_D0N/DSIHOST_D0Npassive
A14DSIHOST_CKN/DSIHOST_CKNpassive
A15DSIHOST_D1N/DSIHOST_D1Npassive
A16VDD1V2_DSI_PHYpassive
A17DDR_DQ0/DDR_DQ0passive
A18DDR_DQ1/DDR_DQ1passive
A19VSSpassive
B10PD2/DCMI_D11/I2C5_SMBA/SDMMC1_CMD/TIM3_ETR/UART4_RX/UART5_RXpassive
B11PE4/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15passive
B12VDDA1V8_DSIpassive
B13DSIHOST_D0P/DSIHOST_D0Ppassive
B14DSIHOST_CKP/DSIHOST_CKPpassive
B15DSIHOST_D1P/DSIHOST_D1Ppassive
B16VDD1V2_DSI_REGpassive
B17DDR_DQ3/DDR_DQ3passive
B18DDR_DQ7/DDR_DQ7passive
B19DDR_DQS0N/DDR_DQS0Npassive
C10PC12/DCMI/DEBUG/I2S3/RCC/SAI4/SDMMC1/SPI3/UART5/USART3passive
C11PC8/DCMI_D2/DEBUG_TRACED0/SDMMC1_D0/TIM3_CH3/TIM8_CH3/UART4_TX/UART5_DE/UART5_RTS/USART6_CKpassive
C12VSS_DSIpassive
C13VSS_DSIpassive
C14VSS_DSIpassive
C15VSS_DSIpassive
C16VSS_DSIpassive
C17VSSpassive
C18DDR_DQM0/DDR_DQM0passive
C19DDR_DQS0P/DDR_DQS0Ppassive
D10PC6/DCMI/DFSDM1/DSIHOST/HDP/I2S2/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6passive
D11PC10/DCMI/DEBUG/DFSDM1/I2S3/LTDC/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3passive
D12NJTRST/DEBUG_JTRSTpassive
D13JTDI/DEBUG_JTDIpassive
D14JTDO-TRACESWO/DEBUG_JTDO-SWOpassive
D15JTMS-SWDIO/DEBUG_JTMS-SWDIOpassive
D16JTCK-SWCLK/DEBUG_JTCK-SWCLKpassive
D17DDR_DQ5/DDR_DQ5passive
D18DDR_DQ2/DDR_DQ2passive
D19DDR_DQ6/DDR_DQ6passive
E10VSSpassive
E11VDDCOREpassive
E12VSSpassive
E13VDDCOREpassive
E14VSSpassive
E15VDDQ_DDRpassive
E16VSSpassive
E17DDR_A7/DDR_A7passive
E18DDR_DQ4/DDR_DQ4passive
F10VDDCOREpassive
F11VSSpassive
F12VDDCOREpassive
F13VSS_PLL2passive
F14VDDQ_DDRpassive
F15VSSpassive
F17DDR_A13/DDR_A13passive
F18DDR_ZQ/DDR_ZQpassive
F19DDR_A3/DDR_A3passive
G10VSSpassive
G11VDDCOREpassive
G12VSSpassive
G13VDD_PLL2passive
G14VSSpassive
G15VDDQ_DDRpassive
G16DDR_RESETN/DDR_RESETNpassive
G17DDR_A9/DDR_A9passive
G18DDR_A2/DDR_A2passive
G19~{DDR_BA0}/~{DDR_BA0}passive
H10VDDCOREpassive
H11VSSpassive
H12VDDCOREpassive
H13VSSpassive
H14VDDQ_DDRpassive
H15VSSpassive
H17DDR_A5/DDR_A5passive
H18DDR_A0/DDR_A0passive
H19DDR_ODT/DDR_ODTpassive
J10VSSpassive
J11VDDCOREpassive
J12VSSpassive
J13VDDCOREpassive
J14VSSpassive
J15VDDQ_DDRpassive
J16~{DDR_BA2}/~{DDR_BA2}passive
J17DDR_WEN/DDR_WENpassive
J18DDR_CSN/DDR_CSNpassive
J19DDR_DTO1/DDR_DTO1passive
K10VDDCOREpassive
K11VSSpassive
K12VDDCOREpassive
K13VSSpassive
K14VDDQ_DDRpassive
K15VSSpassive
K17DDR_CASN/DDR_CASNpassive
K18DDR_DTO0/DDR_DTO0passive
K19DDR_CLKN/DDR_CLKNpassive
L10VSSpassive
L11VDDCOREpassive
L12VSSpassive
L13VDDCOREpassive
L14VSSpassive
L15VDDQ_DDRpassive
L16DDR_A15/DDR_A15passive
L17DDR_A12/DDR_A12passive
L18DDR_RASN/DDR_RASNpassive
L19DDR_CLKP/DDR_CLKPpassive
M10VDDCOREpassive
M11VSSpassive
M12VDDCOREpassive
M13VSSpassive
M14VDDQ_DDRpassive
M15VSSpassive
M17DDR_A1/DDR_A1passive
M18DDR_A11/DDR_A11passive
M19DDR_A10/DDR_A10passive
N10VSSpassive
N11VDDCOREpassive
N12VSSpassive
N13VDDCOREpassive
N14VSSpassive
N15VDDQ_DDRpassive
N16DDR_A6/DDR_A6passive
N17~{DDR_BA1}/~{DDR_BA1}passive
N18DDR_A14/DDR_A14passive
N19DDR_ATO/DDR_ATOpassive
P10VDDpassive
P11VSSpassive
P12VDDCOREpassive
P13VSSpassive
P14VDDQ_DDRpassive
P15VSSpassive
P17DDR_A4/DDR_A4passive
P18DDR_DQ8/DDR_DQ8passive
P19DDR_CKE/DDR_CKEpassive
R10VSSpassive
R11VDDpassive
R12VSSpassive
R13VDDCOREpassive
R14VSSpassive
R15VDDQ_DDRpassive
R16VSSpassive
R17DDR_A8/DDR_A8passive
R18DDR_DQ10/DDR_DQ10passive
T10PE7/DFSDM1_DATIN2/FMC_D4/FMC_DA4/~{QUADSPI_BK2_IO0}/TIM1_ETR/TIM3_ETR/UART7_RXpassive
T11PE8/DFSDM1_CKIN2/FMC_D5/FMC_DA5/~{QUADSPI_BK2_IO1}/TIM1_CH1N/UART7_TXpassive
T12PB6/CEC/DCMI/DFSDM1/FDCAN2/I2C1/I2C4/QUADSPI/TIM16/TIM4/UART5/USART1passive
T13PB2/DEBUG/DFSDM1/I2S3/I2S/QUADSPI/SAI1/SPI3/UART4/USART1passive
T14PG9/DAC1/DCMI/DEBUG/FMC/LTDC/QUADSPI/SAI2/SPDIFRX/USART6passive
T15BYPASS_REG1V8passive
T16PA10/DCMI_D1/I2S3_WS/~{LTDC_B1}/~{SAI4_FS_B}/~{SPI3_NSS}/TIM1_CH3/USART1_RX/USB_OTG_HS_IDpassive
T17DDR_DQ9/DDR_DQ9passive
T18DDR_DQ13/DDR_DQ13passive
T19DDR_DQS1N/DDR_DQS1Npassive
U10PF8/DEBUG_TRACED12/~{QUADSPI_BK1_IO0}/~{SAI1_SCK_B}/SPI5_MISO/TIM13_CH1/TIM16_CH1N/UART7_DE/UART7_RTSpassive
U11PD12/FMC/I2C1/I2C4/LPTIM1/LPTIM2/QUADSPI/SAI2/TIM4/USART3passive
U12PD13/DSIHOST_TE/FMC_A18/I2C1_SDA/I2C4_SDA/I2S3_MCK/LPTIM1_OUT/~{QUADSPI_BK1_IO3}/SAI2_SCK_A/TIM4_CH2passive
U13VSS_USBHSpassive
U14VSS_USBHSpassive
U15OTG_VBUS/USB_OTG_HS_VBUSpassive
U16PA12/FDCAN1_TX/I2C5_SDA/I2C6_SDA/LTDC_R5/~{SAI2_FS_B}/TIM1_ETR/UART4_TX/USART1_DE/USART1_RTSpassive
U17VSSpassive
U18DDR_DQM1/DDR_DQM1passive
U19DDR_DQS1P/DDR_DQS1Ppassive
V10PE10/DFSDM1_DATIN4/FMC_D7/FMC_DA7/~{QUADSPI_BK2_IO3}/TIM1_CH2N/UART7_CTSpassive
V11VDDA1V8_REGpassive
V12VSS_USBHSpassive
V13USB_DM2/USBH_HS2_DM/USB_OTG_HS_DMpassive
V14USB_DP1/USBH_HS1_DPpassive
V15VSS_USBHSpassive
V16USB_RREFpassive
V17PA11/ADC1/ADC2/FDCAN1/I2C5/I2C6/I2S2/LTDC/SPI2/TIM1/UART4/USART1passive
V18DDR_DQ14/DDR_DQ14passive
V19DDR_DQ11/DDR_DQ11passive
W10PG7/DCMI/DEBUG/LTDC/QUADSPI/SAI1/UART8/USART6passive
W11VDDA1V1_REGpassive
W12VDD3V3_USBHSpassive
W13USB_DP2/USBH_HS2_DP/USB_OTG_HS_DPpassive
W14USB_DM1/USBH_HS1_DMpassive
W15VDD3V3_USBFSpassive
W16DDR_VREF/DDR_VREFpassive
W17DDR_DQ15/DDR_DQ15passive
W18DDR_DQ12/DDR_DQ12passive
W19VSSpassive

Provenance

Credit
Celestial Altium Library by Issus and contributors (https://github.com/issus/altium-library)
Licence
LicenseRef-Celestial-Altium
Link method
none
Cross-check
not confirmed