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ST MICROELECTRONICS STM32MP157A_4

celestial-altium-MCU_STM32

Symbol

361 pins
Schematic symbol for ST MICROELECTRONICS STM32MP157A_4
Units
11
Kind
part
Grid
on 1.27 mm

Footprint

none
no footprint linked

This symbol carries no usable footprint reference, so nothing is linked. Generating one is a better answer than guessing.

3D model

none
no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

No footprint is linked, so there is nothing to cross-check.

PinNameType
A1VSSpassive
A2PH5/I2C2_SDA/~{SAI4_SD_B}/~{SPI5_NSS}passive
A3PE13/DCMI_D6/DFSDM1_CKIN5/FMC_D10/FMC_DA10/HDP_HDP2/LTDC_DE/~{SAI2_FS_B}/SPI4_MISO/TIM1_CH3passive
A4PE11/ADC1/ADC2/DCMI/DFSDM1/FMC/LTDC/SAI2/SPI4/TIM1/USART6passive
A5PF1/FMC_A1/I2C2_SCL/SDMMC3_CDIR/SDMMC3_CMDpassive
A7PD5/~{FMC_NWE}/SDMMC3_D2/USART2_TXpassive
A8PA9/DAC1_EXTI9/DCMI_D0/I2C3_SMBA/I2S2_CK/LTDC_R5/SDMMC2_CDIR/SDMMC2_D5/SPI2_SCK/TIM1_CH2/USART1_TXpassive
B1PH15/ADC1_EXTI15/ADC2_EXTI15/DCMI_D11/LTDC_G4/TIM8_CH3Npassive
B2PH12/DCMI_D3/HDP_HDP2/I2C1_SDA/I2C4_SDA/LTDC_R6/TIM5_CH3passive
B3PH4/I2C2_SCL/LTDC_G4/LTDC_G5passive
B4PE12/DFSDM1_DATIN5/FMC_D9/FMC_DA9/~{LTDC_B4}/~{SAI2_SCK_B}/SDMMC1_D0DIR/SPI4_SCK/TIM1_CH3Npassive
B5PD10/DFSDM1/FMC/I2C5/I2S3/LTDC/RTC/SAI3/SPI3/TIM16/USART3passive
B6PD4/DFSDM1_CKIN0/~{FMC_NOE}/SAI3_FS_A/SDMMC3_D1/USART2_DE/USART2_RTSpassive
B7PG15/ADC1/ADC2/DCMI/DEBUG/I2C2/SAI1/SDMMC3/USART6passive
B8PD0/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4passive
B9PD1/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4passive
C1PI0/DCMI_D13/I2S2_WS/LTDC_G5/~{SPI2_NSS}/TIM5_CH4passive
C2PH10/DCMI_D1/I2C1_SMBA/I2C4_SMBA/LTDC_R4/TIM5_CH1passive
C3PH14/DCMI_D4/FDCAN1_RX/LTDC_G3/TIM8_CH2N/UART4_RXpassive
C4PH11/ADC1_EXTI11/ADC2_EXTI11/DCMI_D2/I2C1_SCL/I2C4_SCL/LTDC_R5/TIM5_CH2passive
C5PH9/DAC1_EXTI9/DCMI_D0/I2C3_SMBA/LTDC_R3/TIM12_CH2passive
C6PE14/FMC/LTDC/SAI2/SDMMC1/SPI4/TIM1/UART8passive
C7VSSpassive
C8PE1/DCMI_D3/~{FMC_NBL1}/I2S2_MCK/LPTIM1_IN2/~{SAI3_SD_B}/UART8_TXpassive
C9PE3/DEBUG_TRACED0/FMC_A19/~{SAI1_SD_B}/SDMMC2_CK/~{TIM15_BKIN}passive
D1PH13/FDCAN1_TX/LTDC_G2/TIM8_CH1N/UART4_TXpassive
D2PD6/DCMI/DFSDM1/FMC/I2S3/LTDC/SAI1/SPI3/TIM16/USART2passive
D3PE15/ADC1/ADC2/FMC/HDP/LTDC/TIM15/TIM1/UART8/USART2passive
D4VSSpassive
D5PH8/DCMI_HSYNC/I2C3_SDA/LTDC_R2/TIM5_ETRpassive
D6PE0/DCMI/FMC/I2S3/LPTIM1/LPTIM2/SAI2/SAI4/SPI3/TIM4/UART8passive
D7PF5/FMC_A5/SDMMC3_D2/USART2_TXpassive
D8PF0/FMC_A0/I2C2_SDA/SDMMC3_CKIN/SDMMC3_D0passive
D9PF4/FMC_A4/SDMMC3_D1/SDMMC3_D123DIR/USART2_RXpassive
E1PI3/DCMI_D10/I2S2_SDO/SPI2_MOSI/TIM8_ETRpassive
E2PI2/DCMI_D9/I2S2_SDI/LTDC_G7/SPI2_MISO/TIM8_CH4passive
E3PI1/DCMI_D8/I2S2_CK/LTDC_G6/SPI2_SCK/~{TIM8_BKIN2}passive
E4PI4/DCMI_D5/~{LTDC_B4}/SAI2_MCLK_A/~{TIM8_BKIN}passive
F2PI7/DCMI_D7/~{LTDC_B7}/SAI2_FS_A/TIM8_CH3passive
F3PI5/DCMI_VSYNC/~{LTDC_B5}/SAI2_SCK_A/TIM8_CH1passive
F4PI6/DCMI_D6/~{LTDC_B6}/SAI2_SD_A/TIM8_CH2passive
G1PZ1/I2C2_SDA/I2C4_SDA/I2C5_SDA/I2C6_SDA/I2S1_SDI/SPI1_MISO/SPI6_MISO/USART1_RXpassive
G2PZ4/I2C2_SCL/I2C4_SCL/I2C5_SCL/I2C6_SCLpassive
G3PZ0/I2C2_SCL/I2C6_SCL/I2S1_CK/SPI1_SCK/SPI6_SCK/USART1_CKpassive
G4PZ3/I2C2_SDA/I2C4_SDA/I2C5_SDA/I2C6_SDA/I2S1_WS/~{SPI1_NSS}/~{SPI6_NSS}/USART1_CTS/~{USART1_NSS}passive
H1PZ6/I2C2_SCL/I2C4_SMBA/I2C6_SCL/I2S1_MCK/USART1_CK/USART1_RXpassive
H2PZ5/I2C2_SDA/I2C4_SDA/I2C5_SDA/I2C6_SDA/USART1_DE/USART1_RTSpassive
H3VSSpassive
H4PI9/DAC1_EXTI9/FDCAN1_RX/HDP_HDP1/LTDC_VSYNC/UART4_RXpassive
J2PD15/ADC1_EXTI15/ADC2_EXTI15/FMC_D1/FMC_DA1/LTDC_R1/SAI3_MCLK_A/TIM4_CH4/UART8_CTSpassive
J3PZ7/I2C2_SDA/I2C6_SDA/USART1_TXpassive
J4PZ2/I2C2_SCL/I2C4_SMBA/I2C5_SMBA/I2C6_SCL/I2S1_SDO/SPI1_MOSI/SPI6_MOSI/USART1_TXpassive
K1PD9/DAC1_EXTI9/DCMI_HSYNC/DFSDM1_DATIN3/FMC_D14/FMC_DA14/~{LTDC_B0}/~{SAI3_SD_B}/USART3_RXpassive
K2PC13/PWR_WKUP3/RTC_LSCO/RTC_TS/TAMP_IN1/TAMP_OUT2/TAMP_OUT3passive
K3PD8/DFSDM1_CKIN3/FMC_D13/FMC_DA13/~{LTDC_B7}/~{SAI3_SCK_B}/SPDIFRX_IN1/USART3_TXpassive
K4PG12/ETH1/FMC/LPTIM1/LTDC/SAI4/SPDIFRX/SPI6/USART6passive
L1PC15-OSC32_OUT/ADC1_EXTI15/ADC2_EXTI15/RCC_OSC32_OUTpassive
L2PC14-OSC32_IN/RCC_OSC32_INpassive
L3PD14/FMC_D0/FMC_DA0/~{SAI3_MCLK_B}/TIM4_CH3/UART8_CTSpassive
L4PI8/PWR_WKUP4/RTC_LSCO/TAMP_IN2/TAMP_OUT3passive
M2BOOT2passive
M3NRSTpassive
M4NRST_COREpassive
N1BOOT0passive
N2PA13/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_1/UART4_TXpassive
N3PWR_LPpassive
N4BOOT1passive
P1PH0-OSC_IN/RCC_OSC_INpassive
P2PH1-OSC_OUT/RCC_OSC_OUTpassive
P3VSSpassive
P4PI11/ADC1_EXTI11/ADC2_EXTI11/I2S_CKIN/LTDC_G6/PWR_WKUP5/RCC_MCO_1passive
R2PWR_ONpassive
R3PDR_ONpassive
R4VREF+passive
T1PI10/ETH1_RX_ER/HDP_HDP0/LTDC_HSYNC/USART3_CTS/~{USART3_NSS}passive
T2PA14/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_2passive
T3PDR_ON_COREpassive
T4PG3/DEBUG_TRACED3/DFSDM1_CKIN1/ETH1_TXD7/FMC_A13/~{TIM8_BKIN2}passive
U1PF3/ETH1_TX_ER/FMC_A3passive
U2PA3/ADC1_INP15/ETH1_COL/LPTIM5_OUT/~{LTDC_B2}/~{LTDC_B5}/PWR_PVD_IN/TIM15_CH2/TIM2_CH4/TIM5_CH4/USART2_RXpassive
U3ANA0/ADC1_INN1/ADC1_INP0/ADC2_INN1/ADC2_INP0passive
U4ANA1/ADC1_INP1/ADC2_INP1passive
V2PG2/DEBUG_TRACED2/ETH1_TXD6/FMC_A12/RCC_MCO_2/~{TIM8_BKIN}passive
V3PA5/ADC1/ADC2/DAC1/I2S1/LTDC/SAI4/SPI1/SPI6/TIM2/TIM8passive
V4PA4/ADC1/ADC2/DAC1/DCMI/HDP/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM5/USART2passive
W1PG1/DEBUG_TRACED1/ETH1_TXD5/FMC_A11passive
W2PC3/ADC1_INN12/ADC1_INP13/DEBUG_TRACECLK/DFSDM1_DATIN1/ETH1_TX_CLK/I2S2_SDO/SPI2_MOSIpassive
W3VSSpassive
W4PH7/DCMI_D9/ETH1_RXD3/I2C3_SCL/SPI5_MISOpassive
Y1PE2/DEBUG_TRACECLK/ETH1_TXD3/FMC_A23/I2C4_SCL/~{QUADSPI_BK1_IO2}/SAI1_CK1/SAI1_MCLK_A/SPI4_SCKpassive
Y2PC2/ADC1_INN11/ADC1_INP12/DCMI_PIXCLK/DFSDM1_CKIN1/DFSDM1_CKOUT/ETH1_TXD2/I2S2_SDI/SPI2_MISOpassive
Y3PB10/DFSDM1/ETH1/I2C2/I2S2/LPTIM2/LTDC/QUADSPI/SPI2/TIM2/USART3passive
Y4PF15/ADC1_EXTI15/ADC2_EXTI15/DEBUG_TRACED7/ETH1_RXD7/FMC_A9/I2C1_SDA/I2C4_SDApassive
Y5PF13/ADC2_INP2/DEBUG_TRACED5/DFSDM1_DATIN3/DFSDM1_DATIN6/ETH1_RXD5/FMC_A7/I2C1_SMBA/I2C4_SMBApassive
Y6PG5/ETH1_CLK125/FMC_A15/TIM1_ETRpassive
Y7PG11/ADC1/ADC2/DCMI/DEBUG/ETH1/LTDC/SPDIFRX/UART4/USART1passive
Y8PB5/DCMI/ETH1/FDCAN2/I2C1/I2C4/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM17/TIM3/UART5passive
Y9PF12/ADC1_INN2/ADC1_INP6/DEBUG_TRACED4/ETH1_RXD4/FMC_A6passive
1A2VDDCOREpassive
1A3VSSpassive
1A4VDDCOREpassive
1A5VSSpassive
1A6VDDCOREpassive
1A7VSSpassive
1A8VDDQ_DDRpassive
1B1VDDCOREpassive
1B2VSSpassive
1B3VDDCOREpassive
1B4VSSpassive
1B5VDDCOREpassive
1B6VSSpassive
1B7VDDQ_DDRpassive
1B8VSSpassive
1B9VDDQ_DDRpassive
1C1VSSpassive
1C2VDDCOREpassive
1C3VSSpassive
1C4VDDCOREpassive
1C5VSSpassive
1C6VDDCOREpassive
1C7VSSpassive
1C8VDDQ_DDRpassive
1C9VSSpassive
1D1VDDCOREpassive
1D2VSSpassive
1D3VDDCOREpassive
1D4VSSpassive
1D5VDDCOREpassive
1D6VSSpassive
1D7VDDCOREpassive
1D8VSSpassive
1D9VDDQ_DDRpassive
1E1VSSpassive
1E2VDDCOREpassive
1E3VSSpassive
1E4VDDCOREpassive
1E5VSSpassive
1E6VDDCOREpassive
1E7VSSpassive
1E8VDDQ_DDRpassive
1E9VSSpassive
1F1VBATpassive
1F2VSSpassive
1F3VDDpassive
1F4VSSpassive
1F5VDDCOREpassive
1F6VSSpassive
1F7VDDCOREpassive
1F8VSSpassive
1F9VDDQ_DDRpassive
1G1VSS_ANApassive
1G2VDD_ANApassive
1G3VSSpassive
1G4VDDpassive
1G5VSSpassive
1G6VDDCOREpassive
1G7VSSpassive
1G8VDDQ_DDRpassive
1G9VSSpassive
1H1VDDApassive
1H2VSSApassive
1H3VDDpassive
1H4VSSpassive
1H5VDDpassive
1H6VSSpassive
1H7VDDCOREpassive
1H8VSSpassive
1H9VDDQ_DDRpassive
1J2VDDpassive
1J3VSSpassive
1J4VDDpassive
1J5VSSpassive
1J6VDDpassive
1J7VSSpassive
1J8VDDQ_DDRpassive
A10PG6/DCMI_D12/DEBUG_TRACED14/LTDC_R7/SDMMC2_CMD/~{TIM17_BKIN}passive
A11PB3/DEBUG/I2S1/I2S3/SAI4/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART7passive
A13PA8/I2C3/I2S3/LTDC/RCC/SAI4/SDMMC2/SPI3/TIM1/TIM8/UART7/USART1/USBpassive
A14PF2/FMC_A2/I2C2_SMBA/SDMMC1_D0DIR/SDMMC2_D0DIR/SDMMC3_D0DIRpassive
A16DSIHOST_CKN/DSIHOST_CKNpassive
A17DSIHOST_D1N/DSIHOST_D1Npassive
A19JTDO-TRACESWO/DEBUG_JTDO-SWOpassive
A20JTDI/DEBUG_JTDIpassive
A21DDR_DQ20/DDR_DQ20passive
A22DDR_DQ23/DDR_DQ23passive
A23VSSpassive
AA1PG14/DEBUG/ETH1/FMC/LPTIM1/LTDC/QUADSPI/SAI4/SPI6/USART6passive
AA2PG13/DEBUG/ETH1/FMC/LPTIM1/LTDC/SAI1/SAI4/SPI6/USART6passive
AA3PH3/DFSDM1_CKIN4/ETH1_COL/LTDC_R1/~{QUADSPI_BK2_IO1}/~{SAI2_MCLK_B}passive
AA4PA1/ADC1/ETH1/LPTIM3/LTDC/QUADSPI/SAI2/TIM15/TIM2/TIM5/UART4/USART2passive
AA5VSSpassive
AA6PC1/ADC1/ADC2/DEBUG/DFSDM1/ETH1/I2S2/PWR/SAI1/SDMMC2/SPI2/TAMPpassive
AA7PB1/ADC1_INP5/ADC2_INP5/DFSDM1_DATIN1/ETH1_RXD3/LTDC_G0/LTDC_R6/TIM1_CH3N/TIM3_CH4/TIM8_CH3Npassive
AA8VSSpassive
AA9PE9/DAC1_EXTI9/DFSDM1_CKOUT/FMC_D6/FMC_DA6/~{QUADSPI_BK2_IO2}/TIM1_CH1/UART7_DE/UART7_RTSpassive
AB1PB11/ADC1/ADC2/DFSDM1/DSIHOST/ETH1/I2C2/LPTIM2/LTDC/TIM2/USART3passive
AB2PG4/ETH1_GTX_CLK/FMC_A14/~{TIM1_BKIN2}passive
AB3PA0/ADC1/ETH1/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/TIM8/UART4/USART2passive
AB4PH2/ETH1_CRS/LPTIM1_IN2/LTDC_R0/~{QUADSPI_BK2_IO0}/~{SAI2_SCK_B}passive
AB5PC0/ADC1_INP10/ADC2_INP10/DFSDM1_CKIN0/DFSDM1_DATIN4/LPTIM2_IN2/LTDC_R5/~{QUADSPI_BK2_NCS}/~{SAI2_FS_B}passive
AB6PB0/ADC1/ADC2/DFSDM1/ETH1/LTDC/TIM1/TIM3/TIM8/UART4passive
AB7PC5/ADC1/ADC2/DFSDM1/ETH1/SAI1/SAI4/SPDIFRXpassive
AB8PA7/ADC1/ADC2/ETH1/I2S1/QUADSPI/SAI4/SPI1/SPI6/TIM14/TIM1/TIM3/TIM8passive
AB9PG8/DEBUG/ETH1/LTDC/SAI4/SPDIFRX/SPI6/TIM2/TIM8/USART3/USART6passive
AC1VSSpassive
AC2PG0/DEBUG_TRACED0/DFSDM1_DATIN0/ETH1_TXD4/FMC_A10passive
AC3PA2/ADC1/ETH1/LPTIM4/LTDC/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/USART2passive
AC4PF14/ADC2_INN2/ADC2_INP6/DEBUG_TRACED6/DFSDM1_CKIN6/ETH1_RXD6/FMC_A8/I2C1_SCL/I2C4_SCLpassive
AC5PB12/DFSDM1/ETH1/FDCAN2/I2C2/I2C6/I2S2/SPI2/TIM1/UART5/USART3passive
AC7PC4/ADC1_INP4/ADC2_INP4/DFSDM1_CKIN2/ETH1_RXD0/I2S1_MCK/SPDIFRX_IN2passive
AC8PA6/ADC1/ADC2/DCMI/I2S1/LTDC/SAI4/SPI1/SPI6/TIM13/TIM1/TIM3/TIM8passive
B10PB9/DAC1/DCMI/DFSDM1/FDCAN1/HDP/I2C1/I2C4/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/TIM17/TIM4/UART4passive
B11PC7/DCMI/DFSDM1/HDP/I2S3/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6passive
B12PB15/ADC1/ADC2/DFSDM1/I2S2/RTC/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1passive
B13PB4/DEBUG/I2S1/I2S2/I2S3/SAI4/SDMMC2/SPI1/SPI2/SPI3/SPI6/TIM16/TIM3/UART7passive
B14PC6/DCMI/DFSDM1/DSIHOST/HDP/I2S2/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6passive
B15DSIHOST_D0N/DSIHOST_D0Npassive
B16DSIHOST_CKP/DSIHOST_CKPpassive
B17DSIHOST_D1P/DSIHOST_D1Ppassive
B18VDD_DSIpassive
B19NJTRST/DEBUG_JTRSTpassive
B20JTCK-SWCLK/DEBUG_JTCK-SWCLKpassive
B21DDR_DQ19/DDR_DQ19passive
B22DDR_DQ16/DDR_DQ16passive
B23DDR_DQS2N/DDR_DQS2Npassive
C10PE6/DCMI/DEBUG/FMC/LTDC/SAI1/SAI2/SDMMC1/SDMMC2/SPI4/TIM15/TIM1passive
C11PE5/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15passive
C12VSSpassive
C13PB14/DFSDM1/I2S2/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1/USART3passive
C14VDDA1V8_DSIpassive
C15DSIHOST_D0P/DSIHOST_D0Ppassive
C16VSS_DSIpassive
C17VDD1V2_DSI_PHYpassive
C18VDD1V2_DSI_REGpassive
C19PA15/CEC/ADC1/ADC2/DEBUG/I2S1/I2S3/LTDC/SAI4/SDMMC1/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART4/UART7passive
C20JTMS-SWDIO/DEBUG_JTMS-SWDIOpassive
C21VSSpassive
C22DDR_DQS2P/DDR_DQS2Ppassive
C23DDR_DQM2/DDR_DQM2passive
D10PD7/DEBUG_TRACED6/DFSDM1_CKIN1/DFSDM1_DATIN4/~{FMC_NE1}/I2C2_SCL/SDMMC3_D3/SPDIFRX_IN0/USART2_CKpassive
D11PB7/DCMI_VSYNC/DFSDM1_CKIN5/~{FMC_NL}/I2C1_SDA/I2C4_SDA/SDMMC2_D1/TIM17_CH1N/TIM4_CH2/USART1_RXpassive
D12PD2/DCMI_D11/I2C5_SMBA/SDMMC1_CMD/TIM3_ETR/UART4_RX/UART5_RXpassive
D13PC12/DCMI/DEBUG/I2S3/RCC/SAI4/SDMMC1/SPI3/UART5/USART3passive
D14PD3/DCMI/DFSDM1/FMC/HDP/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/USART2passive
D15PC10/DCMI/DEBUG/DFSDM1/I2S3/LTDC/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3passive
D16PC11/ADC1/ADC2/DCMI/DEBUG/DFSDM1/I2S3/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3passive
D17PC9/DAC1/DCMI/DEBUG/I2C3/I2S/LTDC/QUADSPI/SDMMC1/TIM3/TIM8/UART5passive
D18PC8/DCMI_D2/DEBUG_TRACED0/SDMMC1_D0/TIM3_CH3/TIM8_CH3/UART4_TX/UART5_DE/UART5_RTS/USART6_CKpassive
D19PE4/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15passive
D20DDR_RESETN/DDR_RESETNpassive
D21DDR_DQ22/DDR_DQ22passive
D22DDR_DQ17/DDR_DQ17passive
D23DDR_DQ18/DDR_DQ18passive
E20DDR_A7/DDR_A7passive
E21DDR_DQ3/DDR_DQ3passive
E22DDR_DQ0/DDR_DQ0passive
E23DDR_DQ21/DDR_DQ21passive
F20DDR_A13/DDR_A13passive
F21VSSpassive
F22DDR_DQ1/DDR_DQ1passive
G20DDR_A9/DDR_A9passive
G21DDR_DQ7/DDR_DQ7passive
G22DDR_DQS0P/DDR_DQS0Ppassive
G23DDR_DQS0N/DDR_DQS0Npassive
H20DDR_A5/DDR_A5passive
H21DDR_DQ2/DDR_DQ2passive
H22DDR_DQ6/DDR_DQ6passive
H23DDR_DQM0/DDR_DQM0passive
J20DDR_A2/DDR_A2passive
J21DDR_DQ4/DDR_DQ4passive
J22DDR_DQ5/DDR_DQ5passive
K20DDR_DTO0/DDR_DTO0passive
K21VSSpassive
K22DDR_A3/DDR_A3passive
K23DDR_ZQ/DDR_ZQpassive
L20DDR_A0/DDR_A0passive
L21DDR_DTO1/DDR_DTO1passive
L22DDR_ODT/DDR_ODTpassive
L23~{DDR_BA0}/~{DDR_BA0}passive
M20DDR_WEN/DDR_WENpassive
M21~{DDR_BA2}/~{DDR_BA2}passive
M22DDR_CSN/DDR_CSNpassive
N20DDR_CASN/DDR_CASNpassive
N21DDR_RASN/DDR_RASNpassive
N22DDR_CLKP/DDR_CLKPpassive
N23DDR_CLKN/DDR_CLKNpassive
P20DDR_A15/DDR_A15passive
P21VSSpassive
P22DDR_A1/DDR_A1passive
P23DDR_A12/DDR_A12passive
R20DDR_A11/DDR_A11passive
R21DDR_A14/DDR_A14passive
R22DDR_A10/DDR_A10passive
T20DDR_CKE/DDR_CKEpassive
T21DDR_DQ8/DDR_DQ8passive
T22DDR_DQ10/DDR_DQ10passive
T23DDR_DQ13/DDR_DQ13passive
U20~{DDR_BA1}/~{DDR_BA1}passive
U21DDR_DQ9/DDR_DQ9passive
U22DDR_DQS1P/DDR_DQS1Ppassive
U23DDR_DQS1N/DDR_DQS1Npassive
V20DDR_A4/DDR_A4passive
V21VSSpassive
V22DDR_DQM1/DDR_DQM1passive
W20DDR_A6/DDR_A6passive
W21DDR_DQ11/DDR_DQ11passive
W22DDR_DQ14/DDR_DQ14passive
W23DDR_DQ12/DDR_DQ12passive
Y10PF11/ADC1_EXTI11/ADC1_INP2/ADC2_EXTI11/DCMI_D12/LTDC_G5/~{SAI2_SD_B}/SPI5_MOSIpassive
Y11PH6/DCMI_D8/ETH1_RXD2/I2C2_SMBA/SPI5_SCK/TIM12_CH1passive
Y12PF10/DCMI_D11/LTDC_DE/QUADSPI_CLK/SAI1_D3/SAI1_D4/SAI4_D3/SAI4_D4/~{TIM16_BKIN}passive
Y13PG9/DAC1/DCMI/DEBUG/FMC/LTDC/QUADSPI/SAI2/SPDIFRX/USART6passive
Y14PB6/CEC/DCMI/DFSDM1/FDCAN2/I2C1/I2C4/QUADSPI/TIM16/TIM4/UART5/USART1passive
Y15PE10/DFSDM1_DATIN4/FMC_D7/FMC_DA7/~{QUADSPI_BK2_IO3}/TIM1_CH2N/UART7_CTSpassive
Y16PB2/DEBUG/DFSDM1/I2S3/I2S/QUADSPI/SAI1/SPI3/UART4/USART1passive
Y17PA10/DCMI_D1/I2S3_WS/~{LTDC_B1}/~{SAI4_FS_B}/~{SPI3_NSS}/TIM1_CH3/USART1_RX/USB_OTG_HS_IDpassive
Y18PD12/FMC/I2C1/I2C4/LPTIM1/LPTIM2/QUADSPI/SAI2/TIM4/USART3passive
Y19DDR_ATO/DDR_ATOpassive
Y20DDR_A8/DDR_A8passive
Y21DDR_DQ15/DDR_DQ15passive
Y22DDR_DQ25/DDR_DQ25passive
Y23DDR_DQ24/DDR_DQ24passive
AA10PB13/DFSDM1/ETH1/FDCAN2/I2S2/LPTIM2/SPI2/TIM1/UART5/USART3passive
AA11PE7/DFSDM1_DATIN2/FMC_D4/FMC_DA4/~{QUADSPI_BK2_IO0}/TIM1_ETR/TIM3_ETR/UART7_RXpassive
AA12VSSpassive
AA13PF6/~{QUADSPI_BK1_IO3}/~{SAI1_SD_B}/~{SAI4_SCK_B}/~{SPI5_NSS}/TIM16_CH1/UART7_RXpassive
AA14PF9/DAC1_EXTI9/DEBUG_TRACED13/~{QUADSPI_BK1_IO1}/~{SAI1_FS_B}/SPI5_MOSI/TIM14_CH1/TIM17_CH1N/UART7_CTSpassive
AA15VDD3V3_USBHSpassive
AA16VSS_USBHSpassive
AA17VDD3V3_USBFSpassive
AA18PA11/ADC1/ADC2/FDCAN1/I2C5/I2C6/I2S2/LTDC/SPI2/TIM1/UART4/USART1passive
AA19PD13/DSIHOST_TE/FMC_A18/I2C1_SDA/I2C4_SDA/I2S3_MCK/LPTIM1_OUT/~{QUADSPI_BK1_IO3}/SAI2_SCK_A/TIM4_CH2passive
AA20DDR_DQM3/DDR_DQM3passive
AA21VSSpassive
AA22DDR_DQ31/DDR_DQ31passive
AA23DDR_DQ30/DDR_DQ30passive
AB10PB8/DCMI/DFSDM1/ETH1/FDCAN1/HDP/I2C1/I2C4/LTDC/SDMMC1/SDMMC2/TIM16/TIM4/UART4passive
AB11PG10/DCMI_D2/DEBUG_TRACED10/~{FMC_NE3}/~{LTDC_B2}/LTDC_G3/~{QUADSPI_BK2_IO2}/~{SAI2_SD_B}/UART8_CTSpassive
AB12PF7/~{QUADSPI_BK1_IO2}/~{SAI1_MCLK_B}/SPI5_SCK/TIM17_CH1/UART7_TXpassive
AB13BYPASS_REG1V8passive
AB14VDDA1V8_REGpassive
AB15VDDA1V1_REGpassive
AB16USB_DM2/USBH_HS2_DM/USB_OTG_HS_DMpassive
AB17USB_DM1/USBH_HS1_DMpassive
AB18USB_RREFpassive
AB19PA12/FDCAN1_TX/I2C5_SDA/I2C6_SDA/LTDC_R5/~{SAI2_FS_B}/TIM1_ETR/UART4_TX/USART1_DE/USART1_RTSpassive
AB20DDR_DQ27/DDR_DQ27passive
AB21DDR_DQ26/DDR_DQ26passive
AB22DDR_DQS3P/DDR_DQS3Ppassive
AB23DDR_DQS3N/DDR_DQS3Npassive
AC10PD11/ADC1/ADC2/FMC/I2C1/I2C4/LPTIM2/QUADSPI/SAI2/USART3passive
AC11PF8/DEBUG_TRACED12/~{QUADSPI_BK1_IO0}/~{SAI1_SCK_B}/SPI5_MISO/TIM13_CH1/TIM16_CH1N/UART7_DE/UART7_RTSpassive
AC13PE8/DFSDM1_CKIN2/FMC_D5/FMC_DA5/~{QUADSPI_BK2_IO1}/TIM1_CH1N/UART7_TXpassive
AC14PG7/DCMI/DEBUG/LTDC/QUADSPI/SAI1/UART8/USART6passive
AC16USB_DP2/USBH_HS2_DP/USB_OTG_HS_DPpassive
AC17USB_DP1/USBH_HS1_DPpassive
AC19OTG_VBUS/USB_OTG_HS_VBUSpassive
AC20DDR_VREF/DDR_VREFpassive
AC21DDR_DQ29/DDR_DQ29passive
AC22DDR_DQ28/DDR_DQ28passive
AC23VSSpassive

Provenance

Credit
Celestial Altium Library by Issus and contributors (https://github.com/issus/altium-library)
Licence
LicenseRef-Celestial-Altium
Link method
none
Cross-check
not confirmed