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ST MICROELECTRONICS STM32N655X0

celestial-altium-MCU_STM32

Symbol

262 pins
Schematic symbol for ST MICROELECTRONICS STM32N655X0
Units
10
Kind
part
Grid
on 1.27 mm

Footprint

none
no footprint linked

This symbol carries no usable footprint reference, so nothing is linked. Generating one is a better answer than guessing.

3D model

none
no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

No footprint is linked, so there is nothing to cross-check.

PinNameType
A1PDR_ONpassive
A2PQ6/~{SAI2_SD_B}/TIM8_CH2Npassive
A3OTG2_HSDM/USB2_OTG_HS_DMpassive
A4VDD33USBpassive
A5OTG1_HSDM/USB1_OTG_HS_DMpassive
A6UCPD1_CC1passive
A7PH0-OSC_IN(PH0)/RCC_OSC_INpassive
A8PC10/DCMIPP/FMC/HDP/I2C4/I2S3/I3C2/PSSI/SDMMC1/SPI3/TIM1/UART4/USART3passive
A9PC1/DCMIPP/DCMI/FDCAN1/HDP/I2C1/I2S2/I3C1/PSSI/SDMMC1/SDMMC2/SPI2/TIM17/TIM4/UART4passive
B1PH3/DEBUG_TRACECLK/LTDC_B4/UART7_TXpassive
B2PH6/LTDC_B5/SPI5_NSSpassive
B3OTG2_HSDP/USB2_OTG_HS_DPpassive
B5OTG1_HSDP/USB1_OTG_HS_DPpassive
B6UCPD1_CC2passive
B7PH1-OSC_OUT(PH1)/RCC_OSC_OUTpassive
B8PC11/ADC1/ADC2/DCMIPP/DCMI/HDP/I2C4/I2S3/I3C2/PSSI/SDMMC1/SPI3/UART4/USART3passive
B9PC6/DCMIPP/DCMI/HDP/I2S2/PSSI/SDMMC1/SDMMC2/TIM1/TIM3/TIM9/USART6passive
C1PC15-OSC32_OUT(OSC32_OUT)/ADC1_EXTI15/ADC2_EXTI15/RCC_OSC32_OUTpassive
C2PH8/I3C2_SDA/SPI5_MISOpassive
C3OTG1_ID/USB1_OTG_HS_IDpassive
C5VDDA18USBpassive
C6OTG1_TXRTUNEpassive
C7PC9/AUDIOCLK/DCMIPP/DCMI/HDP/I2C3/LTDC/PSSI/RCC/SDMMC1/TIM3/UART5/UCPD1/USART6passive
C8PC12/DCMIPP/DCMI/DEBUG/FMC/HDP/I2S3/I2S6/PSSI/SDMMC1/SPI3/SPI6/TIM15/TIM1/UART5/USART3passive
C9PC7/DCMIPP/DCMI/DEBUG/HDP/I2S3/PSSI/SDMMC1/SDMMC2/TIM16/TIM3/TIM9/USART6passive
D1PC14-OSC32_IN(OSC32_IN)/RCC_OSC32_INpassive
D2PH7/I3C2_SCL/SPI5_MOSIpassive
D3PQ3/TIM8_CH1passive
D4PQ4/TIM8_CH1Npassive
D5PQ5/~{SAI2_FS_B}/TIM8_CH2passive
D6OTG2_TXRTUNEpassive
D7PC8/DCMIPP/DCMI/DEBUG/FMC/HDP/I2C3/LTDC/PSSI/SDMMC1/TIM3/UART5/UCPD1/USART6passive
D8PH9/DCMIPP/DCMI/FDCAN1/FMC/HDP/I2C1/I3C1/PSSI/SDMMC1/SDMMC2/TIM16/TIM4/UART4/USART3passive
D9PC2/ADF1/DCMIPP/DCMI/FMC/I2S3/MDF1/PSSI/SAI1/SDMMC2/SPI3/USART2passive
E1VBATpassive
E2PWR_ONpassive
E3PQ2/~{SAI2_SCK_B}/TIM8_BKIN2passive
E4PQ1/TIM8_BKINpassive
E5PQ0/DEBUG_TRACECLK/TIM8_ETRpassive
E6OTG2_ID/USB2_OTG_HS_IDpassive
E7PH2/DCMIPP/DCMI/DEBUG/FDCAN1/FMC/PSSI/SDMMC1/TIM15/TIM1/TIM3/UART5passive
E8VDDIO4passive
E9VDDIO5passive
F1V08CAPpassive
F2VSSAPMUpassive
F3PC13/HDP_HDP5/PWR_WKUP3/RTC_OUT1/RTC_TS/TAMP_IN1/TAMP_OUT2passive
F4PH4/LTDC_R4/TAMP_IN4/TAMP_OUT3/UART7_TXpassive
F5PH5/ETH1_MDC/SPI5_SCKpassive
F6VDDA18AONpassive
F7VSSpassive
F8VDDIO4passive
F9VDDIO5passive
G1VDDA18PMUpassive
G2VFBSMPSpassive
G3NRSTpassive
G4BOOT0passive
G5PQ7/~{SAI2_MCLK_B}/TAMP_IN2/TAMP_OUT1/TIM8_CH3passive
G6VSSAONpassive
H1VSSSMPSpassive
H2VSSSMPSpassive
H3VSSSMPSpassive
H4VSSSMPSpassive
H5VSSSMPSpassive
H6VSSSMPSpassive
J1VLXSMPSpassive
J2VLXSMPSpassive
J3VLXSMPSpassive
J4VLXSMPSpassive
J5VLXSMPSpassive
J6VLXSMPSpassive
K1VDDSMPSpassive
K2VDDSMPSpassive
K3VDDSMPSpassive
K4VDDSMPSpassive
K5VDDSMPSpassive
K6VDDSMPSpassive
L1PG7/DCMIPP_D13/DCMI_D13/DEBUG_TRACECLK/ETH1_PHY_INTN/PSSI_D13/SAI1_MCLK_A/USART6_CKpassive
L2PF4/ADC1/DCMIPP/DCMI/ETH1/HDP/I2S1/I2S3/I2S6/LPTIM3/LTDC/PSSI/SPI1/SPI3/SPI6/TIM5/USART2passive
L3PG6/DCMIPP_D12/DCMI_D12/ETH1_MII_CRS/LTDC_B3/PSSI_D12/TIM17_BKIN/USART6_CKpassive
L4PF10/DCMIPP/DCMI/ETH1/LTDC/MDF1/PSSI/SAI1/TIM16/UART7/UCPD1passive
L5PF6/ADC1/ADC2/ETH1/GFXTIM/HDP/I2S6/LPTIM3/LTDC/SPI1/SPI4/SPI5/TIM15/TIM1/TIM2/TIM5/USART2passive
L6VDDCOREpassive
M1PF7/ADC1/ADC2/ETH1/GFXTIM/HDP/I2S1/LTDC/SPI1/TIM1/TIM3/TIM9/UART4passive
M2PF3/ADC1_INP16/DCMIPP_HSYNC/DCMI_HSYNC/ETH1_PPS_OUT/FDCAN3_RX/FMC_NL/LTDC_R4/PSSI_DE/USART2_RTSpassive
M3PF5/DCMIPP/DCMI/ETH1/FMC/LPTIM2/LTDC/PSSI/SAI2/TIM1/USART3passive
M4PG5/ETH1_MII_RX_ER/LTDC_B1/TIM1_ETR/USART2_CTS/USART2_NSSpassive
M5VDDA18PLLpassive
M6VSSApassive
M7VDDCOREpassive
M8VSSpassive
M9VDDCOREpassive
N1PF15/ADC1/ADC2/ETH1/LTDC/SPI5/USART1passive
N2PF14/ADC2/ETH1/LTDC/SPI5/TIM2/USART1passive
N3PF8/DEBUG_TRACECLK/ETH1_MII_RXD2/ETH1_RGMII_RXD2/FMC_NWE/LTDC_R6/UART9_TXpassive
N4PF2/ETH1_RGMII_CLK125/FDCAN3_TX/FMC_NWAIT/I2S2_CK/LTDC_B1/SPI2_SCK/TIM1_CH3N/USART2_CTS/USART2_NSSpassive
N5VSSpassive
N6VDDA18ADCpassive
N7VSSpassive
N8VDDCOREpassive
N9VSSpassive
P1PF9/DEBUG_TRACED0/ETH1_MII_RXD3/ETH1_RGMII_RXD3/LTDC_HSYNCpassive
P2PG4/ETH1_MII_TXD3/ETH1_RGMII_TXD3/LTDC_B0/TIM1_BKIN2passive
P3PF11/ADC1/ADC2/DCMIPP/ETH1/LTDC/PSSI/SAI2/SPI5passive
P4PF1/DCMIPP/DCMI/ETH1/LPTIM1/LPTIM2/PSSI/TIM4/UART8/UART9/UCPD1passive
P5CSI_REXTpassive
P6PG14/DCMIPP/DCMI/DEBUG/FMC/I2S6/LPTIM1/LTDC/PSSI/SPI6/TIM8/USART10/USART2/USART6passive
P7PA9/ADC1/ADC2/DCMIPP/DCMI/FMC/HDP/I2C3/I2S2/I3C2/LPUART1/LTDC/PSSI/SPI2/TIM1/USART1passive
P8PA6/BOOT1/ADC1/ADC2/DCMIPP/DCMI/HDP/I2S1/I2S6/I3C1/LPTIM3/LTDC/MDIOS/PSSI/SPI1/SPI6/TIM13/TIM1/TIM3passive
P9PA1/ADC1/ADC2/DCMIPP/DCMI/FMC/HDP/LPTIM3/LTDC/PSSI/SAI2/TIM15/TIM2/TIM5/UART4/USART2passive
R1PG3/DCMIPP_HSYNC/DCMI_HSYNC/DEBUG_TRACED1/ETH1_MII_TXD2/ETH1_RGMII_TXD2/PSSI_DE/USART2_TXpassive
R2PF13/ADC2/DCMIPP/DCMI/ETH1/PSSI/SPI5/USART1passive
R3PF0/DCMIPP/DCMI/ETH1/LPTIM5/PSSI/TIM4/UART8/UART9/UCPD1passive
R4VDDCSIpassive
R5VDDA18CSIpassive
R6PG15/ADC1/ADC2/DCMIPP/DCMI/ETH1/FMC/LTDC/PSSI/SPI1/SPI4/SPI5/TIM1/USART3passive
R7PA10/ADC1/ADC2/DCMIPP/DCMI/FMC/HDP/LPUART1/LTDC/MDIOS/PSSI/PWR/TIM1/USART1passive
R8PA5/ADC2/DCMIPP/DCMI/FMC/HDP/I2S1/I2S6/I3C1/LTDC/PSSI/PWR/SPI1/SPI6/TIM10/TIM2/TIM9passive
R9PG1/DCMIPP/DCMI/FMC/LTDC/PSSI/SAI1/SPI5/TIM13/TIM16/UART7passive
T1PF12/ADC1/DCMIPP/DCMI/ETH1/PSSI/SPI5/USART1passive
T2VREF-passive
T3CSI_CKPpassive
T4CSI_D1Ppassive
T5CSI_D0Ppassive
T6PA14(JTCK/DEBUG_JTCK-SWCLK/HDP_HDP6/SWCLK)passive
T7PA11/ADC1/ADC2/FDCAN1/FMC/HDP/I2S2/LPUART1/LTDC/SPI2/TIM1/UART4/USART1passive
T8PA2/ADC1/ADC2/FMC/HDP/LPTIM3/LTDC/MDIOS/PWR/SAI2/TIM15/TIM2/TIM5/USART2passive
T9PG12/FMC_A18/LTDC_G0/~{SAI1_MCLK_B}/SPI5_SCK/TIM17_CH1/UART7_TXpassive
U1VSSpassive
U2VREF+passive
U3CSI_CKNpassive
U4CSI_D1Npassive
U5CSI_D0Npassive
U6PA13(JTMS/DEBUG_JTMS-SWDIO/HDP_HDP5/SWDIO)passive
U7PA12/ADC1/ADC2/FDCAN1/FMC/HDP/I2S2/LPUART1/LTDC/SAI2/SPI2/TIM1/UART4/USART1passive
U8PA8/ADC1/ADC2/FMC/HDP/I2C3/I3C2/LTDC/RCC/TIM11/TIM1/UART7/USART1passive
U9PG13/DCMIPP/DCMI/FMC/LPTIM1/LPTIM2/LTDC/PSSI/SAI2/TIM4/USART3passive
A10PC4/FMC/HDP/I2S2/LPTIM2/LTDC/SDMMC2/SPI2/TIM12/TIM1/UART4/USART1/USART3passive
A11PE13/ADF1_CCK0/FMC_SDNCAS/I2C4_SCL/~{SAI2_FS_B}/SPI4_MISO/TIM1_CH3passive
A12PE15/ADC1/ADC2/FMC/GFXTIM/I2C4/SDMMC1/SPI5/TIM1/USART10/USART2passive
A13PD10/DEBUG/FMC/GFXTIM/HDP/I2S1/MDF1/SAI2/SPDIFRX1/TIM1/UCPD1passive
A14PD1/ETH1_MDC/FDCAN1_TX/FMC_A7/FMC_A23/UART4_TXpassive
A15PE8/DCMIPP_D4/DCMI_D4/FMC_A12/MDF1_SDI0/PSSI_D4/TIM1_CH1N/UART7_TX/USART3_TXpassive
A16PE9/FMC_A14/FMC_BA0/MDF1_CKI4/TIM1_CH1/UART7_RTSpassive
A17VSSpassive
B10PC5/DCMIPP_D2/DCMI_D2/FMC_NWE/I2S1_WS/PSSI_D2/~{SAI2_SD_B}/SDMMC2_D1/SPI1_NSSpassive
B11PE14/ADF1_CCK1/FMC_NWE/FMC_SDNE0/GFXTIM_FCKCAL/GFXTIM_LCKCAL/I2C4_SDA/~{SAI2_MCLK_B}/SPI4_MOSI/TIM1_CH4passive
B12PE12/FDCAN3_RX/FMC_SDNRAS/MDF1_SDI5/~{SAI2_SCK_B}/SPI4_SCK/TIM1_CH3Npassive
B13PE7/FMC_A4/FMC_A20/MDF1_CKI0/~{SAI2_SD_B}/TIM1_ETR/UART7_RXpassive
B14PD15/ADC1_EXTI15/ADC2_EXTI15/FMC_A8/I2C2_SDA/LTDC_R2/USART10_TXpassive
B15PD4/DCMIPP_D9/DCMI_D9/FMC_A11/I2C2_SDA/PSSI_D9/SPI5_MISO/TAMP_IN7/TAMP_OUT8/TIM1_BKIN2/USART6_RTSpassive
B16PE10/DCMIPP/DCMI/DEBUG/FMC/MDF1/PSSI/TIM1/UART7/USART3passive
B17PB14/DCMIPP/DCMI/FMC/LPTIM1/LTDC/PSSI/TIM8/USART10/USART6passive
C10PC0/DCMIPP/DCMI/FMC/HDP/I2S1/I2S3/I2S6/LPTIM4/LTDC/MDF1/PSSI/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART7passive
C11PE5/DCMIPP/DCMI/FDCAN2/FMC/HDP/I2C1/I3C1/LPUART1/PSSI/TIM16/TIM4/UART5/USART1passive
C12PD2/ADF1/DEBUG/FMC/HDP/I2S2/MDF1/MDIOS/PWR/SAI1/SDMMC2/SPI2/TIM15/TIM1passive
C13PD12/DCMIPP/DCMI/ETH1/FMC/HDP/MDF1/PSSI/SAI1/SPDIFRX1/UCPD1passive
C14PD14/FMC_A9/I2C2_SCL/USART10_RXpassive
C15PB13/DEBUG/FMC/I2S6/LPTIM1/LTDC/SDMMC2/SPI6/TIM8/USART10/USART6passive
C16PB2/ADF1/FMC/HDP/I2S3/LTDC/MDF1/RTC/SAI1/SPI3/TIM1passive
C17PD13/DCMIPP/DCMI/FMC/LPTIM1/LTDC/PSSI/SAI2/TIM4/UART9/UCPD1passive
D10PE4/DCMIPP/DCMI/I2S6/LPTIM1/LTDC/PSSI/SDMMC2/SPDIFRX1/SPI6/USART10/USART6passive
D11PE6/DCMIPP/DCMI/FMC/HDP/I2C1/I3C1/LPUART1/PSSI/TIM17/TIM4/UART5/USART1passive
D12PD6/FMC_A1/FMC_A17/FMC_ALE/HDP_HDP2/I2S2_SDI/SPI2_MISO/TIM15_CH2/TIM1_CH1passive
D13PD0/DCMIPP_HSYNC/DCMI_HSYNC/FDCAN1_RX/FMC_A6/FMC_A22/PSSI_DE/TIM1_ETR/UART4_RX/UART9_CTSpassive
D14PD5/DCMIPP_PIXCLK/DCMI_PIXCLK/FMC_D6/FMC_DA6/PSSI_PDCK/SDMMC2_D7/TIM1_CH4N/USART2_TXpassive
D15PB9/DCMIPP/DCMI/FMC/I2S1/LPTIM1/PSSI/SDMMC2/SPDIFRX1/SPI1/USART10passive
D16PB8/DCMIPP/DCMI/FMC/I2S1/PSSI/SAI2/SDMMC2/SPDIFRX1/SPI1/USART6passive
D17PB15/ADC1_EXTI15/ADC2_EXTI15/FMC_D0/FMC_DA0/I2S6_WS/LTDC_G4/SPDIFRX1_IN2/SPI6_NSS/USART6_RTSpassive
E10PC3/DCMIPP_D2/DCMI_D2/FMC_D8/FMC_DA8/I2S1_SDO/PSSI_D2/SDMMC2_CMD/SPDIFRX1_IN0/SPI1_MOSI/USART2_CKpassive
E11PE11/ADC1_EXTI11/ADC2_EXTI11/FDCAN3_TX/FMC_SDNWE/LTDC_VSYNC/MDF1_CKI5/~{SAI2_SD_B}/SPI4_NSS/TIM1_CH2passive
E12PD7/DCMIPP/DCMI/FMC/HDP/I2S2/I2S3/PSSI/SPI2/SPI3/TIM15/TIM1passive
E13PD3/DCMIPP_D14/ETH1_PHY_INTN/FMC_A10/I2C2_SMBA/PSSI_D14/USART10_RX/USART6_CTSpassive
E14PD8/DCMIPP_D11/DCMI_D11/FMC_NBL0/LTDC_R7/PSSI_D11/SPDIFRX1_IN1/TAMP_IN3/TAMP_OUT4/USART3_TXpassive
E15PB0/ADF1/DCMIPP/DCMI/DEBUG/FMC/MDF1/PSSI/SAI1/SPI4/TIM15/TIM1passive
E16PB7/ADF1/DCMIPP/DCMI/DEBUG/FMC/MDF1/PSSI/SAI1/SAI2/SPI4/TIM15/TIM1passive
E17PB6/ADF1/DCMIPP/DCMI/DEBUG/FMC/MDF1/PSSI/SAI1/SPI4/TIM15passive
F10VSSpassive
F11VSSpassive
F12VSSpassive
F13PB3/DEBUG/FMC/GFXTIM/HDP/MDF1/SAI2/TIM1/USART1passive
F14PE3/DEBUG_TRACED0/FMC_D12/FMC_DA12/LPTIM5_ETR/MDF1_CKI2/~{SAI1_SD_B}/TIM15_BKINpassive
F15PE2/ADF1/DEBUG/FMC/LPTIM5/MDF1/SAI1/SPI4/TIM1/UCPD1passive
F16PE0/DCMIPP/DCMI/FMC/LPTIM1/LPTIM2/PSSI/SAI2/TAMP/TIM4/UART8/USART3passive
F17PE1/DCMIPP_D8/DCMI_D8/FMC_D10/FMC_DA10/LPTIM1_IN2/LPTIM2_CH2/PSSI_D8/UART8_TX/USART3_TXpassive
G12VSSpassive
G13VDDpassive
G14PD11/ADC1/ADC2/DCMIPP/FMC/I2C4/I2S2/PSSI/SDMMC1/SPI2/UCPD1passive
G15PP7/FMC_D23/XSPIM_P1_IO7passive
G16PP6/FMC_D22/XSPIM_P1_IO6passive
G17PP0/FMC_D16/XSPIM_P1_IO0passive
H12VDDpassive
H13VDDpassive
H14PD9/DCMIPP_D11/DCMI_D11/FMC_SDCLK/LTDC_R1/PSSI_D11/TAMP_IN5/TAMP_OUT6/USART3_RXpassive
H15PP4/FMC_D20/XSPIM_P1_IO4passive
H16PP1/FMC_D17/XSPIM_P1_IO1passive
H17PP15/ADC1_EXTI15/ADC2_EXTI15/FMC_D31/LTDC_B5/XSPIM_P1_IO15passive
J12VDDpassive
J13VDDpassive
J14PP5/FMC_D21/XSPIM_P1_IO5passive
J15PP12/FMC_D28/XSPIM_P1_IO12passive
J16PP3/FMC_D19/XSPIM_P1_IO3passive
J17PP2/FMC_D18/XSPIM_P1_IO2passive
K12VSSpassive
K13VDDpassive
K14PP13/FMC_D29/XSPIM_P1_IO13passive
K15PO5/FMC_A25/FMC_NBL3/XSPIM_P1_NCLKpassive
K16PO1/FMC_A23/XSPIM_P1_NCS2passive
K17PO2/FMC_A24/LTDC_B7/XSPIM_P1_DQS0passive
L12VDDCOREpassive
L13VDDIO2passive
L14VDDIO2passive
L15PP11/ADC1_EXTI11/ADC2_EXTI11/FMC_D27/XSPIM_P1_IO11passive
L16PP8/FMC_D24/SPI2_MISO/XSPIM_P1_IO8passive
L17PP14/FMC_D30/XSPIM_P1_IO14passive
M10VSSpassive
M11VDDCOREpassive
M12VSSpassive
M13VSSpassive
M14VDDIO2passive
M15VDDIO2passive
M16PO3/FMC_A25/LTDC_G3/XSPIM_P1_DQS1passive
M17PO0/FMC_A22/XSPIM_P1_NCS1passive
N10VDDCOREpassive
N11VSSpassive
N12VDDCOREpassive
N13VDDIO3passive
N14PP9/FMC_D25/SPI2_MOSI/XSPIM_P1_IO9passive
N15PP10/ETH1_MDC/FMC_D26/XSPIM_P1_IO10passive
N16PO4/FMC_A24/FMC_NBL2/LTDC_B4/XSPIM_P1_CLKpassive
N17PN4/XSPIM_P2_IO2passive
P10PB11/ADC1/ADC2/FMC/HDP/I2C2/I3C2/LPTIM2/LTDC/TIM2/USART3passive
P11VDDCOREpassive
P12PA15(JTDI)/ADC1/ADC2/DEBUG/FMC/HDP/I2S1/I2S3/I2S6/LTDC/SPI1/SPI3/SPI6/TIM2/UART4/UART7passive
P13VDDIO3passive
P14PN12/XSPIM_P2_NCS2passive
P15PN6/XSPIM_P2_CLKpassive
P16PN8/XSPIM_P2_IO4passive
P17PN0/FMC_A25/XSPIM_P2_DQS0passive
R10PB12/FDCAN2/FMC/HDP/I2C2/I2S2/LPTIM2/LTDC/SPI2/TIM1/UART5/USART3passive
R11PB1/FDCAN2_TX/FMC_NOE/HDP_HDP1/LTDC_R1/TIM1_CH3N/TIM3_CH4/TIM9_CH2/USART2_TXpassive
R12PA7/HDP/I2S1/I2S6/LTDC/SPI1/SPI6/TIM14/TIM1/TIM3/USART1passive
R13PG0/ETH1_PHY_INTN/LTDC_R0/LTDC_VSYNC/TIM12_CH1/TIM1_CH4N/UART9_RXpassive
R14PA3/FMC_A17/FMC_ALE/~{SAI1_SD_B}/SPI5_NSS/TIM16_CH1/UART7_RXpassive
R15PN3/FMC_A22/XSPIM_P2_IO1passive
R16PN5/XSPIM_P2_IO3passive
R17PN1/FMC_A24/XSPIM_P2_NCS1passive
T10PG10/DCMIPP/DCMI/FDCAN2/FMC/HDP/I2S2/LPTIM2/LTDC/PSSI/SPI2/TIM1/UART5/USART3passive
T11PG2/DCMIPP/DCMI/FMC/LTDC/PSSI/SAI1/SAI2/SPI5/TIM14/TIM17/UART7/USART3passive
T12PB4(NJTRST)/DCMIPP/DCMI/DEBUG/FMC/HDP/I2S1/I2S2/I2S3/I2S6/LPTIM4/LTDC/PSSI/SDMMC2/SPI1/SPI2/SPI3passive
T13PG9/FMC_D8/FMC_DA8/LTDC_R7passive
T14PG8/FMC/HDP/I2S2/LTDC/PWR/RTC/SAI1/SDMMC2/SPI2/TIM12/TIM1/UART4/USART1passive
T15PN9/DCMIPP_D5/DCMI_D5/PSSI_D5/XSPIM_P2_IO5passive
T16PN7/XSPIM_P2_NCLKpassive
T17PN2/FMC_A23/XSPIM_P2_IO0passive
U10PA0/ADC1/ADC2/FMC/HDP/I2S6/LTDC/PWR/SAI2/SDMMC2/SPI6/TIM15/TIM2/TIM5/TIM9/UART4/USART2passive
U11PB10/ADC1/ADC2/FMC/HDP/I2C2/I2S2/I3C2/LPTIM2/LTDC/SPI2/TIM2/USART3passive
U12PB5(JTDO/TRACESWO)/DCMIPP/DCMI/DEBUG/FDCAN2/FMC/HDP/I2C1/I2S1/I2S3/I2S6/LPTIM4/LTDC/PSSI/SPI1/SPI3passive
U13PG11/ADC1_EXTI11/ADC2_EXTI11/ETH1_MDC/LTDC_R6/UART7_RXpassive
U14PA4/DCMIPP_D3/DCMI_D3/FMC_A13/PSSI_D3/SPI5_MOSI/USART6_RXpassive
U15PN10/LTDC_B4/XSPIM_P2_IO6passive
U16PN11/ADC1_EXTI11/ADC2_EXTI11/LTDC_B6/XSPIM_P2_IO7passive
U17VSSpassive

Provenance

Credit
Celestial Altium Library by Issus and contributors (https://github.com/issus/altium-library)
Licence
LicenseRef-Celestial-Altium
Link method
none
Cross-check
not confirmed