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ST MICROELECTRONICS STM32N657L0

celestial-altium-MCU_STM32

Symbol

221 pins
Schematic symbol for ST MICROELECTRONICS STM32N657L0
Units
9
Kind
part
Grid
on 1.27 mm

Footprint

none
no footprint linked

This symbol carries no usable footprint reference, so nothing is linked. Generating one is a better answer than guessing.

3D model

none
no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

No footprint is linked, so there is nothing to cross-check.

PinNameType
A1PDR_ONpassive
A2OTG1_TXRTUNEpassive
A3OTG1_HSDP/USB1_OTG_HS_DPpassive
A4UCPD1_CC1passive
A5PH0-OSC_IN(PH0)/RCC_OSC_INpassive
A6PC12/DCMIPP/DCMI/DEBUG/FMC/HDP/I2S3/I2S6/PSSI/SDMMC1/SPI3/SPI6/TIM15/TIM1/UART5/USART3passive
A7PC1/DCMIPP/DCMI/FDCAN1/HDP/I2C1/I2S2/I3C1/PSSI/SDMMC1/SDMMC2/SPI2/TIM17/TIM4/UART4passive
A8PC6/DCMIPP/DCMI/HDP/I2S2/PSSI/SDMMC1/SDMMC2/TIM1/TIM3/TIM9/USART6passive
A9PE13/ADF1_CCK0/FMC_SDNCAS/I2C4_SCL/~{SAI2_FS_B}/SPI4_MISO/TIM1_CH3passive
B2OTG1_ID/USB1_OTG_HS_IDpassive
B3OTG1_HSDM/USB1_OTG_HS_DMpassive
B4UCPD1_CC2passive
B5PH1-OSC_OUT(PH1)/RCC_OSC_OUTpassive
B6PC11/ADC1/ADC2/DCMIPP/DCMI/HDP/I2C4/I2S3/I3C2/PSSI/SDMMC1/SPI3/UART4/USART3passive
B7PH9/DCMIPP/DCMI/FDCAN1/FMC/HDP/I2C1/I3C1/PSSI/SDMMC1/SDMMC2/TIM16/TIM4/UART4/USART3passive
B8PC7/DCMIPP/DCMI/DEBUG/HDP/I2S3/PSSI/SDMMC1/SDMMC2/TIM16/TIM3/TIM9/USART6passive
B9PE6/DCMIPP/DCMI/FMC/HDP/I2C1/I3C1/LPUART1/PSSI/TIM17/TIM4/UART5/USART1passive
C1OTG2_HSDP/USB2_OTG_HS_DPpassive
C2OTG2_HSDM/USB2_OTG_HS_DMpassive
C3VDD33USBpassive
D1PC15-OSC32_OUT(OSC32_OUT)/ADC1_EXTI15/ADC2_EXTI15/RCC_OSC32_OUTpassive
D4VDDA18USBpassive
D5PC9/AUDIOCLK/DCMIPP/DCMI/HDP/I2C3/LTDC/PSSI/RCC/SDMMC1/TIM3/UART5/UCPD1/USART6passive
D6PC10/DCMIPP/FMC/HDP/I2C4/I2S3/I3C2/PSSI/SDMMC1/SPI3/TIM1/UART4/USART3passive
D7PH2/DCMIPP/DCMI/DEBUG/FDCAN1/FMC/PSSI/SDMMC1/TIM15/TIM1/TIM3/UART5passive
D8PE11/ADC1_EXTI11/ADC2_EXTI11/FDCAN3_TX/FMC_SDNWE/LTDC_VSYNC/MDF1_CKI5/~{SAI2_SD_B}/SPI4_NSS/TIM1_CH2passive
D9PE5/DCMIPP/DCMI/FDCAN2/FMC/HDP/I2C1/I3C1/LPUART1/PSSI/TIM16/TIM4/UART5/USART1passive
E1PC14-OSC32_IN(OSC32_IN)/RCC_OSC32_INpassive
E2OTG2_TXRTUNEpassive
E4OTG2_ID/USB2_OTG_HS_IDpassive
F1VBATpassive
F2NRSTpassive
F4BOOT0passive
F6PC8/DCMIPP/DCMI/DEBUG/FMC/HDP/I2C3/LTDC/PSSI/SDMMC1/TIM3/UART5/UCPD1/USART6passive
F7VDDIO4passive
F8VDDIO4passive
F9PE14/ADF1_CCK1/FMC_NWE/FMC_SDNE0/GFXTIM_FCKCAL/GFXTIM_LCKCAL/I2C4_SDA/~{SAI2_MCLK_B}/SPI4_MOSI/TIM1_CH4passive
G1V08CAPpassive
G2VFBSMPSpassive
G4PWR_ONpassive
G6VSSAONpassive
H1VDDA18PMUpassive
H2VSSAPMUpassive
H4PC13/HDP_HDP5/PWR_WKUP3/RTC_OUT1/RTC_TS/TAMP_IN1/TAMP_OUT2passive
H6VDDA18AONpassive
J1VSSSMPSpassive
J2VSSSMPSpassive
J3VSSSMPSpassive
J4VSSSMPSpassive
J5VSSSMPSpassive
K1VLXSMPSpassive
K2VLXSMPSpassive
K3VLXSMPSpassive
K4VLXSMPSpassive
K5VLXSMPSpassive
L1VDDSMPSpassive
L2VDDSMPSpassive
L3VDDSMPSpassive
L4VDDSMPSpassive
L5VDDSMPSpassive
M1PF4/ADC1/DCMIPP/DCMI/ETH1/HDP/I2S1/I2S3/I2S6/LPTIM3/LTDC/PSSI/SPI1/SPI3/SPI6/TIM5/USART2passive
M2PF10/DCMIPP/DCMI/ETH1/LTDC/MDF1/PSSI/SAI1/TIM16/UART7/UCPD1passive
M4PF6/ADC1/ADC2/ETH1/GFXTIM/HDP/I2S6/LPTIM3/LTDC/SPI1/SPI4/SPI5/TIM15/TIM1/TIM2/TIM5/USART2passive
M6VDDA18PLLpassive
N1PG6/DCMIPP_D12/DCMI_D12/ETH1_MII_CRS/LTDC_B3/PSSI_D12/TIM17_BKIN/USART6_CKpassive
N2PG5/ETH1_MII_RX_ER/LTDC_B1/TIM1_ETR/USART2_CTS/USART2_NSSpassive
N4PF5/DCMIPP/DCMI/ETH1/FMC/LPTIM2/LTDC/PSSI/SAI2/TIM1/USART3passive
N6VSSApassive
P1PF3/ADC1_INP16/DCMIPP_HSYNC/DCMI_HSYNC/ETH1_PPS_OUT/FDCAN3_RX/FMC_NL/LTDC_R4/PSSI_DE/USART2_RTSpassive
P2PF14/ADC2/ETH1/LTDC/SPI5/TIM2/USART1passive
P4PF2/ETH1_RGMII_CLK125/FDCAN3_TX/FMC_NWAIT/I2S2_CK/LTDC_B1/SPI2_SCK/TIM1_CH3N/USART2_CTS/USART2_NSSpassive
P6VDDA18ADCpassive
P7VDDCOREpassive
P8VSSpassive
P9VDDCOREpassive
R1PF15/ADC1/ADC2/ETH1/LTDC/SPI5/USART1passive
R2PF7/ADC1/ADC2/ETH1/GFXTIM/HDP/I2S1/LTDC/SPI1/TIM1/TIM3/TIM9/UART4passive
R4PF8/DEBUG_TRACECLK/ETH1_MII_RXD2/ETH1_RGMII_RXD2/FMC_NWE/LTDC_R6/UART9_TXpassive
T1PF11/ADC1/ADC2/DCMIPP/ETH1/LTDC/PSSI/SAI2/SPI5passive
T2PF9/DEBUG_TRACED0/ETH1_MII_RXD3/ETH1_RGMII_RXD3/LTDC_HSYNCpassive
T4PG4/ETH1_MII_TXD3/ETH1_RGMII_TXD3/LTDC_B0/TIM1_BKIN2passive
T5PG3/DCMIPP_HSYNC/DCMI_HSYNC/DEBUG_TRACED1/ETH1_MII_TXD2/ETH1_RGMII_TXD2/PSSI_DE/USART2_TXpassive
T6CSI_REXTpassive
T7PG14/DCMIPP/DCMI/DEBUG/FMC/I2S6/LPTIM1/LTDC/PSSI/SPI6/USART10/USART2/USART6passive
T8PA11/ADC1/ADC2/FDCAN1/FMC/HDP/I2S2/LPUART1/LTDC/SPI2/TIM1/UART4/USART1passive
T9PA8/ADC1/ADC2/FMC/HDP/I2C3/I3C2/LTDC/RCC/TIM11/TIM1/UART7/USART1passive
U1PF1/DCMIPP/DCMI/ETH1/LPTIM1/LPTIM2/PSSI/TIM4/UART8/UART9/UCPD1passive
U2PF12/ADC1/DCMIPP/DCMI/ETH1/PSSI/SPI5/USART1passive
U3PF0/DCMIPP/DCMI/ETH1/LPTIM5/PSSI/TIM4/UART8/UART9/UCPD1passive
V1PF13/ADC2/DCMIPP/DCMI/ETH1/PSSI/SPI5/USART1passive
V2VREF-passive
V3CSI_D1Npassive
V4CSI_CKNpassive
V5CSI_D0Npassive
V6VDDA18CSIpassive
V7PA14(JTCK/DEBUG_JTCK-SWCLK/HDP_HDP6/SWCLK)passive
V8PA12/ADC1/ADC2/FDCAN1/FMC/HDP/I2S2/LPUART1/LTDC/SAI2/SPI2/TIM1/UART4/USART1passive
V9PA9/ADC1/ADC2/DCMIPP/DCMI/FMC/HDP/I2C3/I2S2/I3C2/LPUART1/LTDC/PSSI/SPI2/TIM1/USART1passive
W1VSSpassive
W2VREF+passive
W3CSI_D1Ppassive
W4CSI_CKPpassive
W5CSI_D0Ppassive
W6VDDCSIpassive
W7PA13(JTMS/DEBUG_JTMS-SWDIO/HDP_HDP5/SWDIO)passive
W8PG15/ADC1/ADC2/DCMIPP/DCMI/ETH1/FMC/LTDC/PSSI/SPI1/SPI4/SPI5/TIM1/USART3passive
W9PA10/ADC1/ADC2/DCMIPP/DCMI/FMC/HDP/LPUART1/LTDC/MDIOS/PSSI/PWR/TIM1/USART1passive
A10PD6/FMC_A1/FMC_A17/FMC_ALE/HDP_HDP2/I2S2_SDI/SPI2_MISO/TIM15_CH2/TIM1_CH1passive
A11PD12/DCMIPP/DCMI/ETH1/FMC/HDP/MDF1/PSSI/SAI1/SPDIFRX1/UCPD1passive
A12PD15/ADC1_EXTI15/ADC2_EXTI15/FMC_A8/I2C2_SDA/LTDC_R2/USART10_TXpassive
A13PE8/DCMIPP_D4/DCMI_D4/FMC_A12/MDF1_SDI0/PSSI_D4/TIM1_CH1N/UART7_TX/USART3_TXpassive
A14PB15/ADC1_EXTI15/ADC2_EXTI15/FMC_D0/FMC_DA0/I2S6_WS/LTDC_G4/SPDIFRX1_IN2/SPI6_NSS/USART6_RTSpassive
A15PD5/DCMIPP_PIXCLK/DCMI_PIXCLK/FMC_D6/FMC_DA6/PSSI_PDCK/SDMMC2_D7/TIM1_CH4N/USART2_TXpassive
A16PB13/DEBUG/FMC/I2S6/LPTIM1/LTDC/SDMMC2/SPI6/USART10/USART6passive
A17PD11/ADC1/ADC2/DCMIPP/FMC/I2C4/I2S2/PSSI/SDMMC1/SPI2/UCPD1passive
A18PE0/DCMIPP/DCMI/FMC/LPTIM1/LPTIM2/PSSI/SAI2/TAMP/TIM4/UART8/USART3passive
A19VSSpassive
B10PD2/ADF1/DEBUG/FMC/HDP/I2S2/MDF1/MDIOS/PWR/SAI1/SDMMC2/SPI2/TIM15/TIM1passive
B11PE7/FMC_A4/FMC_A20/MDF1_CKI0/~{SAI2_SD_B}/TIM1_ETR/UART7_RXpassive
B12PD0/DCMIPP_HSYNC/DCMI_HSYNC/FDCAN1_RX/FMC_A6/FMC_A22/PSSI_DE/TIM1_ETR/UART4_RX/UART9_CTSpassive
B13PD4/DCMIPP_D9/DCMI_D9/FMC_A11/I2C2_SDA/PSSI_D9/SPI5_MISO/TAMP_IN7/TAMP_OUT8/TIM1_BKIN2/USART6_RTSpassive
B14PD8/DCMIPP_D11/DCMI_D11/FMC_NBL0/LTDC_R7/PSSI_D11/SPDIFRX1_IN1/TAMP_IN3/TAMP_OUT4/USART3_TXpassive
B15PB9/DCMIPP/DCMI/FMC/I2S1/LPTIM1/PSSI/SDMMC2/SPDIFRX1/SPI1/USART10passive
B16PB2/ADF1/FMC/HDP/I2S3/LTDC/MDF1/RTC/SAI1/SPI3/TIM1passive
B17PB3/DEBUG/FMC/GFXTIM/HDP/MDF1/SAI2/TIM1/USART1passive
B18PE1/DCMIPP_D8/DCMI_D8/FMC_D10/FMC_DA10/LPTIM1_IN2/LPTIM2_CH2/PSSI_D8/UART8_TX/USART3_TXpassive
B19PE2/ADF1/DEBUG/FMC/LPTIM5/MDF1/SAI1/SPI4/TIM1/UCPD1passive
C17PB14/DCMIPP/DCMI/FMC/LPTIM1/LTDC/PSSI/USART10/USART6passive
C18PE3/DEBUG_TRACED0/FMC_D12/FMC_DA12/LPTIM5_ETR/MDF1_CKI2/~{SAI1_SD_B}/TIM15_BKINpassive
C19PB0/ADF1/DCMIPP/DCMI/DEBUG/FMC/MDF1/PSSI/SAI1/SPI4/TIM15/TIM1passive
D10PE12/FDCAN3_RX/FMC_SDNRAS/MDF1_SDI5/~{SAI2_SCK_B}/SPI4_SCK/TIM1_CH3Npassive
D11PD10/DEBUG/FMC/GFXTIM/HDP/I2S1/MDF1/SAI2/SPDIFRX1/TIM1/UCPD1passive
D12PD1/ETH1_MDC/FDCAN1_TX/FMC_A7/FMC_A23/UART4_TXpassive
D13PD3/DCMIPP_D14/ETH1_PHY_INTN/FMC_A10/I2C2_SMBA/PSSI_D14/USART10_RX/USART6_CTSpassive
D14PE10/DCMIPP/DCMI/DEBUG/FMC/MDF1/PSSI/TIM1/UART7/USART3passive
D15PB8/DCMIPP/DCMI/FMC/I2S1/PSSI/SAI2/SDMMC2/SPDIFRX1/SPI1/USART6passive
D16PD13/DCMIPP/DCMI/FMC/LPTIM1/LTDC/PSSI/SAI2/TIM4/UART9/UCPD1passive
D18PP10/ETH1_MDC/FMC_D26/XSPIM_P1_IO10passive
D19PB6/ADF1/DCMIPP/DCMI/DEBUG/FMC/MDF1/PSSI/SAI1/SPI4/TIM15passive
E16PB7/ADF1/DCMIPP/DCMI/DEBUG/FMC/MDF1/PSSI/SAI1/SAI2/SPI4/TIM15/TIM1passive
E18PO3/FMC_A25/LTDC_G3/XSPIM_P1_DQS1passive
E19PP9/FMC_D25/SPI2_MOSI/XSPIM_P1_IO9passive
F10PE15/ADC1/ADC2/FMC/GFXTIM/I2C4/SDMMC1/SPI5/TIM1/USART10/USART2passive
F11PD7/DCMIPP/DCMI/FMC/HDP/I2S2/I2S3/PSSI/SPI2/SPI3/TIM15/TIM1passive
F12VSSpassive
F13PD14/FMC_A9/I2C2_SCL/USART10_RXpassive
F14PE9/FMC_A14/FMC_BA0/MDF1_CKI4/TIM1_CH1/UART7_RTSpassive
F16PO0/FMC_A22/XSPIM_P1_NCS1passive
F18PP1/FMC_D17/XSPIM_P1_IO1passive
F19PP8/FMC_D24/SPI2_MISO/XSPIM_P1_IO8passive
G14PD9/DCMIPP_D11/DCMI_D11/FMC_SDCLK/LTDC_R1/PSSI_D11/TAMP_IN5/TAMP_OUT6/USART3_RXpassive
G16PO5/FMC_A25/FMC_NBL3/XSPIM_P1_NCLKpassive
G18PO2/FMC_A24/LTDC_B7/XSPIM_P1_DQS0passive
G19PP7/FMC_D23/XSPIM_P1_IO7passive
H14VSSpassive
H16VDDIO2passive
H18PP0/FMC_D16/XSPIM_P1_IO0passive
H19PP6/FMC_D22/XSPIM_P1_IO6passive
J14VDDpassive
J16VDDIO2passive
J18PO4/FMC_A24/FMC_NBL2/LTDC_B4/XSPIM_P1_CLKpassive
J19PP5/FMC_D21/XSPIM_P1_IO5passive
K14VDDpassive
K16VDDIO2passive
K18PP2/FMC_D18/XSPIM_P1_IO2passive
K19PP3/FMC_D19/XSPIM_P1_IO3passive
L14VDDpassive
L16VDDIO2passive
L18PP15/ADC1_EXTI15/ADC2_EXTI15/FMC_D31/LTDC_B5/XSPIM_P1_IO15passive
L19PP4/FMC_D20/XSPIM_P1_IO4passive
M14VDDIO3passive
M16VDDIO3passive
M18PP14/FMC_D30/XSPIM_P1_IO14passive
M19PP13/FMC_D29/XSPIM_P1_IO13passive
N14PO1/FMC_A23/XSPIM_P1_NCS2passive
N16VSSpassive
N18PP12/FMC_D28/XSPIM_P1_IO12passive
N19PP11/ADC1_EXTI11/ADC2_EXTI11/FMC_D27/XSPIM_P1_IO11passive
P10VDDCOREpassive
P11VDDCOREpassive
P12VSSpassive
P13VDDCOREpassive
P14VSSpassive
P16PN1/FMC_A24/XSPIM_P2_NCS1passive
P18PN11/ADC1_EXTI11/ADC2_EXTI11/LTDC_B6/XSPIM_P2_IO7passive
P19PN3/FMC_A22/XSPIM_P2_IO1passive
R16PN7/XSPIM_P2_NCLKpassive
R18PN10/LTDC_B4/XSPIM_P2_IO6passive
R19PN0/FMC_A25/XSPIM_P2_DQS0passive
T10PA6/BOOT1/ADC1/ADC2/DCMIPP/DCMI/HDP/I2S1/I2S6/I3C1/LPTIM3/LTDC/MDIOS/PSSI/SPI1/SPI6/TIM13/TIM1/TIM3passive
T11PG1/DCMIPP/DCMI/FMC/LTDC/PSSI/SAI1/SPI5/TIM13/TIM16/UART7passive
T12PG10/DCMIPP/DCMI/FDCAN2/FMC/HDP/I2S2/LPTIM2/LTDC/PSSI/SPI2/TIM1/UART5/USART3passive
T13PB10/ADC1/ADC2/FMC/HDP/I2C2/I2S2/I3C2/LPTIM2/LTDC/SPI2/TIM2/USART3passive
T14PB5(JTDO/TRACESWO)/DCMIPP/DCMI/DEBUG/FDCAN2/FMC/HDP/I2C1/I2S1/I2S3/I2S6/LTDC/PSSI/SPI1/SPI3/SPI6passive
T15PA15(JTDI)/ADC1/ADC2/DEBUG/FMC/HDP/I2S1/I2S3/I2S6/LTDC/SPI1/SPI3/SPI6/TIM2/UART4/UART7passive
T16PG0/ETH1_PHY_INTN/LTDC_R0/LTDC_VSYNC/TIM12_CH1/TIM1_CH4N/UART9_RXpassive
T18PN9/DCMIPP_D5/DCMI_D5/PSSI_D5/XSPIM_P2_IO5passive
T19PN2/FMC_A23/XSPIM_P2_IO0passive
U17PA3/FMC_A17/FMC_ALE/~{SAI1_SD_B}/SPI5_NSS/TIM16_CH1/UART7_RXpassive
U18PN5/XSPIM_P2_IO3passive
U19PN6/XSPIM_P2_CLKpassive
V10PA5/ADC2/DCMIPP/DCMI/FMC/HDP/I2S1/I2S6/I3C1/LTDC/PSSI/PWR/SPI1/SPI6/TIM10/TIM2/TIM9passive
V11PG12/FMC_A18/LTDC_G0/~{SAI1_MCLK_B}/SPI5_SCK/TIM17_CH1/UART7_TXpassive
V12PA0/ADC1/ADC2/FMC/HDP/I2S6/LTDC/PWR/SAI2/SDMMC2/SPI6/TIM15/TIM2/TIM5/TIM9/UART4/USART2passive
V13PB11/ADC1/ADC2/FMC/HDP/I2C2/I3C2/LPTIM2/LTDC/TIM2/USART3passive
V14PB1/FDCAN2_TX/FMC_NOE/HDP_HDP1/LTDC_R1/TIM1_CH3N/TIM3_CH4/TIM9_CH2/USART2_TXpassive
V15PA7/HDP/I2S1/I2S6/LTDC/SPI1/SPI6/TIM14/TIM1/TIM3/USART1passive
V16PG9/FMC_D8/FMC_DA8/LTDC_R7passive
V17PG8/FMC/HDP/I2S2/LTDC/PWR/RTC/SAI1/SDMMC2/SPI2/TIM12/TIM1/UART4/USART1passive
V18PN8/XSPIM_P2_IO4passive
V19PN4/XSPIM_P2_IO2passive
W10PA2/ADC1/ADC2/FMC/HDP/LPTIM3/LTDC/MDIOS/PWR/SAI2/TIM15/TIM2/TIM5/USART2passive
W11PG13/DCMIPP/DCMI/FMC/LPTIM1/LPTIM2/LTDC/PSSI/SAI2/TIM4/USART3passive
W12PA1/ADC1/ADC2/DCMIPP/DCMI/FMC/HDP/LPTIM3/LTDC/PSSI/SAI2/TIM15/TIM2/TIM5/UART4/USART2passive
W13PB12/FDCAN2/FMC/HDP/I2C2/I2S2/LPTIM2/LTDC/SPI2/TIM1/UART5/USART3passive
W14PG2/DCMIPP/DCMI/FMC/LTDC/PSSI/SAI1/SAI2/SPI5/TIM14/TIM17/UART7/USART3passive
W15PB4(NJTRST)/DCMIPP/DCMI/DEBUG/FMC/HDP/I2S1/I2S2/I2S3/I2S6/LTDC/PSSI/SDMMC2/SPI1/SPI2/SPI3/SPI6passive
W16PG11/ADC1_EXTI11/ADC2_EXTI11/ETH1_MDC/LTDC_R6/UART7_RXpassive
W17PA4/DCMIPP_D3/DCMI_D3/FMC_A13/PSSI_D3/SPI5_MOSI/USART6_RXpassive
W18PN12/XSPIM_P2_NCS2passive
W19VSSpassive

Provenance

Credit
Celestial Altium Library by Issus and contributors (https://github.com/issus/altium-library)
Licence
LicenseRef-Celestial-Altium
Link method
none
Cross-check
not confirmed