TI MSPM0G110X WCSP-28 YCJ

celestial-altium-MCU_TI

Symbol

28 pins

Units: 1
Kind: part
Grid: on 1.27 mm

Footprint

none

no footprint linked

This symbol carries no usable footprint reference, so nothing is linked. Generating one is a better answer than guessing.

3D model

none

no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

No footprint is linked, so there is nothing to cross-check.

Pin	Name	Type
A1	PB19/PB19/SPI0.POCI/TIMG8.CCP1/UART0.CTS/TIMG7.CCP1/ADC1.6	passive
A2	PA23/PA23/UART2.TX/TIMA0.CCP3/TIMG0.CCP0/UART3.CTS/TIMG7.CCP0/TIMG8.CCP0/VREF.VREF+/CS3	passive
A3	PA24/PA24/UART2.RX/SPI0.CS2_POCI2/TIMA0.CCP3_CMPL/TIMG0.CCP1/UART3.RTS/TIMG7.CCP1/TIMA1.CCP1/ADC0.3	passive
A4	VCORE	passive
B1	PA18/PA18/UART1.RX/SPI1.PICO/I2C1.SDA/TIMA0.CCP3_CMPL/TIMG7.CCP1/TIMA1.CCP1/ADC1.3/GPAMP.IN-	passive
B2	PB23/PB23/SPI1.SCLK/TIMA0.FAULT0/TIMA1.FAULT0	passive
B3	PA26/PA26/UART3.TX/SPI1.CS0/TIMG8.CCP0/TIMA0.FAULT0/TIMA1.FAULT0/TIMG7.CCP0/ADC0.1/GPAMP.IN+	passive
B4	NRST/SYSCTL.NRST	passive
C1	PA19/PA19/DEBUGSS.SWDIO	passive
C2	PA22/PA22/UART2.RX/TIMG8.CCP1/UART1.RTS/TIMA0.CCP1/TIMG6.CCP1/ADC0.7/ADC1.8/GPAMP.OUT/CLK/CCP0	passive
C3	PA27/PA27/RTC.RTC_OUT/SPI1.CS1_POCI1/TIMG8.CCP1/TIMA0.FAULT2/TIMA1.FAULT2/TIMG7.CCP1/ADC0.0	passive
C4	VDD	passive
D1	PA20/PA20/DEBUGSS.SWCLK	passive
D2	PA21/PA21/UART2.TX/TIMG8.CCP0/UART1.CTS/TIMA0.CCP0/TIMG6.CCP0/ADC1.7/ADC0.8/VREF.VREF-	passive
D3	PA0/PA0/UART0.TX/I2C0.SDA/TIMA0.CCP0/TIMA0.FAULT1/TIMA1.FAULT1/TIMG8.CCP1/SYSCTL.FCC_IN	passive
D4	VSS	passive
E1	PA16/PA16/SPI1.POCI/I2C1.SDA/TIMA1.CCP1/TIMA1.CCP1_CMPL/TIMA0.CCP2_CMPL/SYSCTL.FCC_IN/ADC1.1	passive
E2	PA25/PA25/UART3.RX/SPI1.CS3_CD_POCI3/TIMG12.CCP1/TIMA0.CCP3/TIMA0.CCP1_CMPL/ADC0.2	passive
E3	PA1/PA1/UART0.RX/I2C0.SCL/TIMA0.CCP1/TIMA0.FAULT2/TIMA1.FAULT2/TIMG8.IDX/TIMG8.CCP0	passive
E4	PA2/PA2/TIMG8.CCP1/SPI0.CS0/TIMG7.CCP1/SPI1.CS0/SYSCTL.ROSC	passive
F1	PA15/PA15/UART0.RTS/SPI1.CS2_POCI2/I2C1.SCL/TIMA1.CCP0/TIMG8.IDX/TIMA1.CCP0_CMPL/TIMA0.CCP2/ADC1.0	passive
F2	PA9/PA9/UART1.RX/SPI0.PICO/UART0.CTS/TIMA0.CCP1/RTC/CCP0/CCP1/CLK	passive
F3	PA5/PA5/TIMG8.CCP0/SPI0.PICO/TIMA0.FAULT1/TIMA1.FAULT1/TIMG0.CCP0/TIMG6.CCP0/SYSCTL.HFXIN/FCC	passive
F4	PA3/PA3/TIMG8.CCP0/SPI0.CS1_POCI1/UART2.CTS/TIMA0.CCP2/TIMG7.CCP0/TIMA0.CCP1/I2C1.SDA/SYSCTL.LFXIN	passive
G1	PA10/PA10/UART0.TX/SPI0.POCI/I2C0.SDA/TIMA1.CCP0/TIMG12.CCP0/TIMA0.CCP2/I2C1.SDA/SYSCTL.CLK_OUT	passive
G2	PA11/PA11/UART0.RX/SPI0.SCLK/I2C0.SCL/TIMA1.CCP1/TIMA0.CCP2_CMPL/I2C1.SCL	passive
G3	PA6/PA6/TIMG8.CCP1/SPI0.SCLK/TIMA0.FAULT0/TIMA1.FAULT0/TIMG0.CCP1/SYSCTL.HFCLKIN/TIMG6.CCP1	passive
G4	PA4/PA4/TIMG8.CCP1/SPI0.POCI/UART2.RTS/TIMA0.CCP3/SYSCTL.LFCLKIN/TIMG7.CCP1/I2C1.SCL/SYSCTL.LFXOUT	passive

Provenance

Source: celestial-altium-symbols
Credit: Celestial Altium Library by Issus and contributors (https://github.com/issus/altium-library)
Licence: LicenseRef-Celestial-Altium
Link method: none
Cross-check: not confirmed