TI MSPM0G150X VSSOP-28 DGS28

celestial-altium-MCU_TI

Symbol

28 pins

Units: 1
Kind: part
Grid: on 1.27 mm

Footprint

none

no footprint linked

This symbol carries no usable footprint reference, so nothing is linked. Generating one is a better answer than guessing.

3D model

none

no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

No footprint is linked, so there is nothing to cross-check.

Pin	Name	Type
1	PA26/PA26/UART3.TX/SPI1.CS0/TIMG8.CCP0/TIMA0.FAULT0/TIMA1.FAULT0/TIMG7.CCP0/ADC0.1/COMP0.IN0+	passive
2	PA27/PA27/TIMG8.CCP1/TIMA0.FAULT2/TIMA1.FAULT2/TIMG7.CCP1/ADC0.0/COMP0.IN0-/OPA0.IN0-/RTC/CS1	passive
3	VCORE	passive
4	PA0/PA0/UART0.TX/I2C0.SDA/TIMA0.CCP0/TIMA0.FAULT1/TIMA1.FAULT1/TIMG8.CCP1/SYSCTL.FCC_IN	passive
5	PA1/PA1/UART0.RX/I2C0.SCL/TIMA0.CCP1/TIMA0.FAULT2/TIMA1.FAULT2/TIMG8.IDX/TIMG8.CCP0	passive
6	NRST/SYSCTL.NRST	passive
7	VDD	passive
8	VSS	passive
9	PA2/PA2/TIMG8.CCP1/SPI0.CS0/TIMG7.CCP1/SPI1.CS0/SYSCTL.ROSC	passive
10	PA3/PA3/TIMG8.CCP0/UART2.CTS/TIMA0.CCP2/COMP1.OUT/TIMG7.CCP0/TIMA0.CCP1/I2C1.SDA/SYSCTL.LFXIN/CS1	passive
11	PA4/PA4/TIMG8.CCP1/SPI0.POCI/UART2.RTS/TIMA0.CCP3/SYSCTL.LFCLKIN/TIMG7.CCP1/I2C1.SCL/SYSCTL.LFXOUT	passive
12	PA5/PA5/TIMG8.CCP0/SPI0.PICO/TIMA0.FAULT1/TIMA1.FAULT1/TIMG0.CCP0/TIMG6.CCP0/SYSCTL.HFXIN/FCC	passive
13	PA6/PA6/TIMG8.CCP1/SPI0.SCLK/TIMA0.FAULT0/TIMA1.FAULT0/TIMG0.CCP1/SYSCTL.HFCLKIN/TIMG6.CCP1	passive
14	PA9/PA9/UART1.RX/SPI0.PICO/UART0.CTS/TIMA0.CCP1/RTC/CCP0/CCP1/CLK	passive
15	PA10/PA10/UART0.TX/SPI0.POCI/I2C0.SDA/TIMA1.CCP0/TIMG12.CCP0/TIMA0.CCP2/I2C1.SDA/SYSCTL.CLK_OUT	passive
16	PA11/PA11/UART0.RX/SPI0.SCLK/I2C0.SCL/TIMA1.CCP1/COMP0.OUT/TIMA0.CCP2_CMPL/I2C1.SCL	passive
17	PA14/PA14/UART0.CTS/SPI0.PICO/UART3.TX/TIMG12.CCP0/SYSCTL.CLK_OUT/COMP0.IN2+/ADC0.12	passive
18	PA15/PA15/UART0.RTS/I2C1.SCL/TIMA1.CCP0/TIMG8.IDX/TIMA0.CCP2/ADC1.0/DAC0.OUT/COMP0.IN3+/COMP1.IN3+	passive
19	PA16/PA16/COMP2.OUT/SPI1.POCI/I2C1.SDA/TIMA1.CCP1/ADC1.1/OPA1.OUT/CCP1/CCP2/FCC	passive
20	PA17/PA17/UART1.TX/SPI1.SCLK/I2C1.SCL/TIMA0.CCP3/TIMG7.CCP0/TIMA1.CCP0/ADC1.2/OPA1.IN1-/COMP0.IN1-	passive
21	PA18/PA18/UART1.RX/SPI1.PICO/I2C1.SDA/TIMG7.CCP1/TIMA1.CCP1/ADC1.3/OPA1.IN1+/COMP0.IN1+/GPAMP.IN-	passive
22	PA19/PA19/DEBUGSS.SWDIO	passive
23	PA20/PA20/DEBUGSS.SWCLK	passive
24	PA21/PA21/UART2.TX/TIMG8.CCP0/UART1.CTS/TIMA0.CCP0/TIMG6.CCP0/ADC1.7/ADC0.8/COMP2.IN1-/VREF.VREF-	passive
25	PA22/PA22/UART2.RX/TIMG8.CCP1/UART1.RTS/TIMA0.CCP1/TIMG6.CCP1/ADC0.7/ADC1.8/OPA0.OUT/GPAMP.OUT/CLK	passive
26	PA23/PA23/UART2.TX/TIMA0.CCP3/TIMG0.CCP0/UART3.CTS/TIMG7.CCP0/TIMG8.CCP0/COMP1.IN1-/VREF.VREF+/CS3	passive
27	PA24/PA24/UART2.RX/TIMG0.CCP1/UART3.RTS/TIMG7.CCP1/TIMA1.CCP1/ADC0.3/OPA0.IN1-/CS2/CCP3	passive
28	PA25/PA25/UART3.RX/SPI1.CS3_CD_POCI3/TIMG12.CCP1/TIMA0.CCP3/TIMA0.CCP1_CMPL/ADC0.2/OPA0.IN1+	passive

Provenance

Source: celestial-altium-symbols
Credit: Celestial Altium Library by Issus and contributors (https://github.com/issus/altium-library)
Licence: LicenseRef-Celestial-Altium
Link method: none
Cross-check: not confirmed