TI MSPM0L122X LQFP-64 PM

celestial-altium-MCU_TI

Symbol

64 pins
Schematic symbol for TI MSPM0L122X LQFP-64 PM
Units
2
Kind
part
Grid
on 1.27 mm

Footprint

none
no footprint linked

This symbol carries no usable footprint reference, so nothing is linked. Generating one is a better answer than guessing.

3D model

none
no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

No footprint is linked, so there is nothing to cross-check.

PinNameType
1PB13/PB13/UART3.RX/TIMA0.CCP3/TIMG12.CCP0/TIMA0.CCP1_CMPL/UART4.RTS/SPI1.CS0passive
2PB14/PB14/SPI1.CS3_CD_POCI3/SPI1.POCI/TIMG12.CCP1/TIMA0.CCP0/TIMG8.IDX/SPI0.CS3_CD_POCI3/ADC0.21passive
3PB15/PB15/UART2.TX/SPI1.PICO/UART3.CTS/TIMG8.CCP0/TIMG5.CCP0/I2C2.SCL/ADC0.20passive
4PB16/PB16/UART2.RX/SPI1.SCLK/UART3.RTS/TIMG8.CCP1/TIMG5.CCP1/I2C2.SDA/ADC0.19passive
5PA12/PA12/UART3.CTS/SPI0.SCLK/COMP0.OUT/TIMA0.CCP3/TIMG0.CCP0/UART2.CTS/UART1.CTS/ADC0.18/FCC/CS1passive
6PA13/PA13/UART3.RTS/SPI0.POCI/UART3.RX/TIMG0.CCP1/SPI1.CS0/UART2.TX/UART1.RTS/ADC0.17/COMP0.IN2-passive
7PA14/PA14/UART0.CTS/SPI0.PICO/UART3.TX/TIMG12.CCP0/TIMG12.CCP1/UART2.RX/ADC0.16/COMP0.IN2+/CLK/CS2passive
8PA15/PA15/UART0.RTS/I2C1.SCL/TIMA0.CCP2/I2C2.SCL/TIMG8.IDX/TIMG12.CCP0/UART2.RTS/ADC0.15/COMP0.IN3+passive
9PA16/PA16/COMP0.OUT/SPI1.POCI/I2C1.SDA/I2C2.SDA/TIMG12.CCP1/UART2.CTS/ADC0.14/CCP2/FCCpassive
10PA17/PA17/UART1.TX/SPI1.SCLK/I2C1.SCL/TIMA0.CCP3/TIMG5.CCP0/TIMG8.CCP0/TIMG12.CCP0/ADC0.13passive
11PA18/PA18/UART1.RX/SPI1.PICO/I2C1.SDA/TIMG5.CCP1/TIMG8.CCP1/TIMG12.CCP1/SPI0.CS0/ADC0.12/COMP0.IN1+passive
12PA19/PA19/DEBUGSS.SWDIO/SPI1.POCI/I2C1.SDA/TIMA0.CCP2/TIMG0.CCP0passive
13PA20/PA20/DEBUGSS.SWCLK/SPI1.SCLK/I2C1.SCL/TIMA0.CCP2_CMPL/TIMG0.CCP1passive
14PB17/PB17/UART2.TX/SPI0.PICO/I2C0.SCL/TIMA0.CCP2/TIMG0.CCP0/UART4.TX/TIMG4.CCP0/ADC0.11/CS1passive
15PB18/PB18/UART2.RX/SPI0.SCLK/I2C0.SDA/TIMG0.CCP1/UART4.RX/TIMG4.CCP1/ADC0.10/CCP2/CS2passive
16PB19/PB19/COMP0.OUT/SPI0.POCI/TIMG8.CCP1/UART0.CTS/TIMG5.CCP1/TIMG8.IDX/UART2.CTS/UART4.CTS/ADC0.9passive
17PA21/PA21/UART2.TX/UART1.CTS/TIMA0.CCP0/TIMG4.CCP0/UART2.CTS/UART4.RTS/TIMG8.CCP0/ADC0.8/VREF.VREF-passive
18PA22/PA22/UART2.RX/UART1.RTS/TIMG4.CCP1/TIMA0.CCP1/I2C0.SCL/TIMG8.CCP1/ADC0.7/CS2/CCP0/CLKpassive
19PB20/PB20/SPI1.CS0/TIMG12.CCP0/TIMA0.CCP2/TIMA0.FAULT1/TIMA0.CCP1/UART2.RTS/I2C0.SDA/ADC0.6/CS2passive
20PB21/PB21/UART4.TX/SPI1.POCI/I2C0.SCL/TIMG8.CCP0/UART1.TX/ADC0.25passive
21PB22/PB22/UART4.RX/SPI1.PICO/I2C0.SDA/TIMG8.CCP1/UART1.RX/ADC0.24passive
22PB23/PB23/UART1.CTS/SPI1.SCLK/TIMA0.FAULT0/COMP0.OUTpassive
23PB24/PB24/TIMG12.CCP1/TIMA0.CCP3/UART2.RTS/ADC0.5/CS3/CS1/CCP1passive
24PA23/PA23/UART2.TX/I2C2.SCL/TIMA0.CCP3/TIMG8.CCP0/TIMG5.CCP0/UART3.CTS/TIMG0.CCP0/VREF.VREF+/CS3passive
25PA24/PA24/UART2.RX/I2C2.SDA/TIMG8.CCP1/TIMG5.CCP1/UART3.RTS/TIMG0.CCP1/ADC0.3/CS2/CCP3passive
26PA25/PA25/UART3.RX/TIMG12.CCP1/TIMA0.CCP3/COMP0.OUT/UART2.CTS/UART3.TX/TIMG4.CCP0/ADC0.2/CS3/CCP1passive
27PB25/PB25/UART0.CTS/SPI0.CS0/TIMA0.FAULT0/TIMA0.FAULT1/TIMA0.FAULT2/COMP0.OUT/SYSCTL.FCC_IN/ADC0.4passive
28PB26/PB26/UART0.RTS/SPI0.CS1_POCI1/TIMA0.CCP0/TIMA0.CCP3/TIMG4.CCP0/COMP0.OUT/SYSCTL.FCC_IN/ADC0.23passive
29PB27/PB27/COMP0.OUT/SPI1.CS1_POCI1/TIMA0.CCP0_CMPL/TIMA0.CCP3_CMPL/TIMG4.CCP1/ADC0.22passive
30PA26/PA26/UART3.TX/SPI1.CS0/TIMG8.CCP0/TIMA0.FAULT0/TIMG5.CCP0/UART2.RTS/UART3.RX/TIMG4.CCP1/ADC0.1passive
31PA27/PA27/UART3.RX/TIMG8.CCP1/TIMA0.FAULT2/TIMG5.CCP1/COMP0.OUT/ADC0.0/COMP0.IN0-/CS1/CLK/RTCpassive
32VCOREpassive
33PA0/PA0/UART0.TX/I2C0.SDA/TIMA0.CCP0/TIMA0.FAULT1/SYSCTL.FCC_IN/TIMG8.CCP1/TIMG12.CCP0/TIMG0.CCP0passive
34PA1/PA1/UART0.RX/I2C0.SCL/TIMA0.CCP1/TIMA0.FAULT2/TIMG8.IDX/TIMG8.CCP0/TIMG12.CCP1/TIMG0.CCP1/CS3passive
35PA28/PA28/UART0.TX/I2C0.SDA/TIMA0.CCP3/TIMA0.FAULT0/TIMG5.CCP0/TIMA0.CCP1passive
36PA29/PA29/I2C1.SCL/UART2.RTS/TIMG8.CCP0/TIMG4.CCP0/I2C2.SCL/UART0.CTS/SPI0.CS3_CD_POCI3passive
37PA30/PA30/I2C1.SDA/UART2.CTS/TIMG8.CCP1/TIMG4.CCP1/I2C2.SDA/UART0.RTS/SPI0.CS2_POCI2passive
38NRST/SYSCTL.NRSTpassive
39VBATpassive
40VDDpassive
41VSSpassive
42PA2/PA2/TIMG8.CCP1/SPI0.CS0/TIMG5.CCP1/SPI1.CS0/TIMA0.FAULT0/TIMA0.FAULT1/UART4.CTS/TIMA0.CCP0passive
43PA3/PA3/TIMG8.CCP0/I2C1.SDA/TIMA0.CCP1/COMP0.OUT/TIMG5.CCP0/TIMA0.CCP2/UART2.CTS/UART1.TXpassive
44PA4/PA4/TIMG8.CCP1/SPI0.POCI/I2C1.SCL/SYSCTL.LFCLKIN/TIMG5.CCP1/TIMA0.CCP3/UART2.RTS/UART1.RXpassive
45PA5/PA5/TIMG8.CCP0/SPI0.PICO/I2C1.SDA/TIMG0.CCP0/TIMG4.CCP0/TIMA0.FAULT1/UART0.CTS/UART4.RTSpassive
46PA6/PA6/TIMG8.CCP1/SPI0.SCLK/I2C1.SCL/TIMG0.CCP1/SYSCTL.HFCLKIN/TIMG4.CCP1/TIMA0.FAULT0/UART0.RTSpassive
47PB0/PB0/UART0.TX/SPI1.CS2_POCI2/I2C0.SCL/TIMA0.CCP2/TIMG0.CCP0/SPI0.CS3_CD_POCI3passive
48PB1/PB1/UART0.RX/SPI1.CS3_CD_POCI3/I2C0.SDA/TIMA0.CCP2_CMPL/TIMG0.CCP1/SPI0.CS2_POCI2passive
49PA7/PA7/COMP0.OUT/TIMG8.CCP0/TIMA0.CCP2/TIMG8.IDX/TIMG5.CCP1/TIMA0.CCP1/SPI0.POCI/LFSS.TIO0/CLK/CS2passive
50PB2/PB2/UART3.TX/UART2.CTS/I2C1.SCL/TIMA0.CCP3/UART1.CTS/TIMG4.CCP0/UART2.TX/TIMG12.CCP0passive
51PB3/PB3/UART3.RX/UART2.RTS/I2C1.SDA/UART1.RTS/TIMG4.CCP1/UART2.RX/TIMG12.CCP1/TIMA0.CCP0/SPI0.SCLKpassive
52PB4/PB4/UART1.TX/UART3.CTS/TIMA0.CCP1/TIMA0.CCP2/TIMG0.CCP0/TIMG4.CCP0passive
53PB5/PB5/UART1.RX/UART3.RTS/TIMA0.CCP1_CMPL/TIMA0.CCP2_CMPL/TIMG0.CCP1/TIMG4.CCP1passive
54PA8/PA8/UART1.TX/SPI0.CS0/I2C0.SDA/TIMA0.CCP0/TIMA0.FAULT2/TIMA0.FAULT0/TIMG5.CCP1/SYSCTL.HFCLKINpassive
55PA9/PA9/UART1.RX/SPI0.PICO/I2C0.SCL/TIMA0.CCP1/TIMG5.CCP0/UART4.RTS/UART0.CTS/CCP0/CLK/RTCpassive
56PA10/PA10/UART0.TX/SPI0.POCI/I2C0.SDA/TIMA0.CCP2/TIMG0.CCP0/I2C1.SDA/TIMG12.CCP0/TIMA0.FAULT1/CLKpassive
57PA11/PA11/UART0.RX/SPI0.SCLK/I2C0.SCL/COMP0.OUT/TIMG0.CCP1/I2C1.SCL/TIMG12.CCP1/TIMA0.FAULT0/CCP2passive
58PB6/PB6/UART1.TX/SPI1.CS0/I2C2.SCL/TIMG8.CCP0/UART2.CTS/TIMG4.CCP0/TIMA0.FAULT2/TIMG12.CCP0/CS1passive
59PB7/PB7/UART1.RX/SPI1.POCI/I2C2.SDA/TIMG8.CCP1/UART2.RTS/TIMG4.CCP1/SPI0.CS2_POCI2/TIMG12.CCP1passive
60PB8/PB8/UART1.CTS/SPI1.PICO/I2C2.SCL/TIMA0.CCP0/COMP0.OUT/TIMG4.CCP0passive
61PB9/PB9/UART1.RTS/SPI1.SCLK/I2C2.SDA/TIMA0.CCP0_CMPL/TIMA0.CCP1/TIMG4.CCP1passive
62PB10/PB10/TIMG0.CCP0/TIMG8.CCP0/COMP0.OUT/TIMG4.CCP0/UART4.TX/SPI1.CS3_CD_POCI3passive
63PB11/PB11/TIMG0.CCP1/TIMG8.CCP1/SYSCTL.CLK_OUT/TIMG4.CCP1/UART4.RX/SPI1.CS2_POCI2passive
64PB12/PB12/UART3.TX/TIMA0.CCP2/TIMA0.FAULT1/TIMA0.CCP1/UART4.CTS/SPI1.CS1_POCI1passive

Provenance

Credit
Celestial Altium Library by Issus and contributors (https://github.com/issus/altium-library)
Licence
LicenseRef-Celestial-Altium
Link method
none
Cross-check
not confirmed