Get Trace

TI AM62x AMC

celestial-altium-MPU_TI

Symbol

432 pins
Schematic symbol for TI AM62x AMC
Units
7
Kind
part
Grid
on 1.27 mm

Footprint

none
no footprint linked

This symbol carries no usable footprint reference, so nothing is linked. Generating one is a better answer than guessing.

3D model

none
no 3D model

The footprint references no model, or the referenced model is not in the upstream package set.

Pins and pads

No footprint is linked, so there is nothing to cross-check.

PinNameType
A1VSSpassive
A2WKUP_LFOSC0_XIpassive
A3WKUP_LFOSC0_XOpassive
A4VSSpassive
A5MCU_OSC0_XIpassive
A6MCU_OSC0_XOpassive
A7MCU_GPIO0_11/WKUP_UART0_CTSn/WKUP_TIMER_IO0/MCU_SPI1_CS0passive
A8MCU_GPIO0_5/MCU_UART0_RXDpassive
A9MCU_GPIO0_20/WKUP_I2C0_SDApassive
B1~{MCU_ERROR}passive
B2~{MCU_POR}passive
B4MCU_GPIO0_12/WKUP_UART0_RTSn/WKUP_TIMER_IO1/MCU_SPI1_CLKpassive
B5MCU_GPIO0_9/WKUP_UART0_RXD/MCU_SPI0_CS2passive
B6MCU_GPIO0_6/MCU_UART0_TXDpassive
B7MCU_GPIO0_2/MCU_SPI0_CLKpassive
B8MCU_GPIO0_7/MCU_UART0_CTSn/MCU_TIMER_IO0/MCU_SPI1_D0passive
B9MCU_GPIO0_17/MCU_I2C0_SCLpassive
C1VDDS_DDRpassive
C2DDR0_DQ0passive
C4MCU_GPIO0_14/MCU_MCAN0_RX/MCU_TIMER_IO0/MCU_SPI1_CS3passive
C5MCU_GPIO0_13/MCU_MCAN0_TX/WKUP_TIMER_IO0/MCU_SPI0_CS3passive
C6MCU_GPIO0_10/WKUP_UART0_TXD/MCU_SPI1_CS2passive
C7MCU_GPIO0_22/PMIC_LPM_EN0passive
C8MCU_GPIO0_1/MCU_SPI0_CS1/MCU_OBSCLK0/MCU_SYSCLKOUT0/MCU_EXT_REFCLK0/MCU_TIMER_IO1passive
C9~{MCU_RESET}passive
D1DDR0_DQS0_Ppassive
D2DDR0_DQ4passive
D3DDR0_DQ2passive
D4VSSpassive
D5MCU_GPIO0_15/MCU_MCAN1_TX/MCU_TIMER_IO2/MCU_SPI1_CS1/MCU_EXT_REFCLK0passive
D6MCU_GPIO0_16/MCU_MCAN1_RX/MCU_TIMER_IO3/MCU_SPI0_CS2/MCU_SPI1_CS2/MCU_SPI1_CLKpassive
D7MCU_GPIO0_8/MCU_UART0_RTSn/MCU_TIMER_IO1/MCU_SPI1_D1passive
D8MCU_GPIO0_4/MCU_SPI0_D1passive
D9EMU0passive
E1DDR0_DQS0_Npassive
E2VSSpassive
E3DDR0_DM0passive
E4DDR0_DQ1passive
E5DDR0_DQ3passive
E7MCU_GPIO0_0/MCU_SPI0_CS0/WKUP_TIMER_IO1passive
E8MCU_GPIO0_3/MCU_SPI0_D0passive
E9MCU_GPIO0_19/WKUP_I2C0_SCLpassive
F1DDR0_DQ6passive
F2DDR0_DQ7passive
F3DDR0_DQ5passive
F4VSSpassive
F5DDR0_A0passive
F6VMON_VSYSpassive
F7VPPpassive
F9VSSpassive
G1~{DDR0_CS1}passive
G2~{DDR0_RESET0}passive
G3DDR0_CKE0passive
G4DDR0_A2passive
G5DDR0_A1passive
G6VSSpassive
G7VDDSHV_CANUARTpassive
G8CAP_VDDS_CANUARTpassive
G9VSSpassive
H1VSSpassive
H2DDR0_CKE1passive
H3~{DDR0_CS0}passive
H4DDR0_A3passive
H5DDR0_A5passive
H6VSSpassive
H7VDDSHV_CANUARTpassive
H8VDD_CANUARTpassive
H9VMON_1P8_SOCpassive
J1DDR0_CK0_Ppassive
J2~{DDR0_WE}passive
J3~{DDR0_CAS}passive
J4DDR0_ODT0passive
J5DDR0_A4passive
J6VSSpassive
J7VDDS_OSC0passive
J8VDDS_DDRpassive
J9VDD_COREpassive
K1DDR0_CK0_Npassive
K2DDR0_ODT1passive
K3VSSpassive
K4DDR0_CAL0passive
K5~{DDR0_RAS}passive
K6VSSpassive
K7VDDS_DDRpassive
K8VSSpassive
K9VDDS_DDRpassive
L1VSSpassive
L2~{DDR0_BG1}passive
L3~{DDR0_BA1}passive
L4~{DDR0_BG0}passive
L5~{DDR0_BA0}passive
L6VSSpassive
L7VDDS_DDR_Cpassive
L8VDDS_DDRpassive
L9VDDA_DDR_PLL0passive
M1~{DDR0_ACT}passive
M2DDR0_PARpassive
M3DDR0_A11passive
M6VSSpassive
M7VDDA_TEMP0passive
M8VDD_COREpassive
M9VSSpassive
N1~{DDR0_ALERT}passive
N2DDR0_A7passive
N3DDR0_A10passive
N4DDR0_A9passive
N5DDR0_A13passive
N6VSSpassive
N7VDDSHV4passive
N8CAP_VDDS4passive
N9VDD_COREpassive
P1VSSpassive
P2DDR0_A8passive
P3VSSpassive
P4DDR0_A6passive
P5DDR0_A12passive
P6VSSpassive
P7VDDSHV4passive
P8VDD_COREpassive
P9VDDA_1P8_OLDI0passive
R1DDR0_DQS1_Npassive
R2DDR0_DQ9passive
R3DDR0_DQ8passive
R4DDR0_DM1passive
R5VSSpassive
R7VSSpassive
R8VSSpassive
R9VDDA_1P8_OLDI0passive
T1DDR0_DQS1_Ppassive
T2DDR0_DQ10passive
T3VSSpassive
T4DDR0_DQ14passive
T5DDR0_DQ15passive
T6VSSpassive
T7VSSpassive
T8USB0_RCALIBpassive
T9VSSpassive
U1VDDS_DDRpassive
U2DDR0_DQ11passive
U3DDR0_DQ12passive
U4DDR0_DQ13passive
U5VSSpassive
U6OLDI0_A2Ppassive
U7OLDI0_A2Npassive
U8VSSpassive
U9USB1_VBUSpassive
V1GPIO1_38/MMC0_DAT1/UART3_RTSn/~{EHRPWM1_B}/PR0_PRU0_GPO2/PR0_PRU0_GPI2/SPI1_CS3/SPI2_CS0passive
V2GPIO1_39/MMC0_DAT0/UART3_CTSn/EHRPWM_TZn_IN1/PR0_PRU0_GPO3/PR0_PRU0_GPI3/SPI2_CLKpassive
V3GPIO1_41/MMC0_CMD/I2C3_SDA/~{EHRPWM2_B}/PR0_PRU0_GPO4/PR0_PRU0_GPI4/SPI1_CS2/TIMER_IO5passive
V4GPIO1_32/MMC0_DAT7/UART2_RXD/EHRPWM0_SYNCI/PR0_PRU1_GPO0/PR0_PRU1_GPI0/SPI1_D0/SPI2_CS1passive
V5OLDI0_A1Npassive
V6OLDI0_A1Ppassive
V7OLDI0_CLK0Npassive
V8OLDI0_CLK0Ppassive
V9USB1_RCALIBpassive
W1GPIO1_36/MMC0_DAT3/UART3_RXD/~{EHRPWM0_B}/PR0_PRU0_GPO0/PR0_PRU0_GPI0/SPI1_CS0/SPI2_CS2passive
W2GPIO1_37/MMC0_DAT2/UART3_TXD/EHRPWM1_A/PR0_PRU0_GPO1/PR0_PRU0_GPI1/SPI1_CLK/TIMER_IO0passive
W3GPIO1_34/MMC0_DAT5/UART2_RTSn/EHRPWM_TZn_IN2/PR0_PRU1_GPO2/PR0_PRU1_GPI2/SPI2_D0passive
W4GPIO1_33/MMC0_DAT6/UART2_TXD/EHRPWM0_SYNCO/PR0_PRU1_GPO1/PR0_PRU1_GPI1/SPI1_D1/SPI2_CS3passive
W5OLDI0_A3Ppassive
W6OLDI0_A3Npassive
W7VSSpassive
W8USB1_DMpassive
W9USB1_DPpassive
Y1GPIO1_40/MMC0_CLK/I2C3_SCL/EHRPWM2_A/PR0_PRU1_GPO4/PR0_PRU1_GPI4/SPI1_CS1/TIMER_IO4passive
Y2GPIO1_35/MMC0_DAT4/UART2_CTSn/EHRPWM0_A/PR0_PRU1_GPO3/PR0_PRU1_GPI3/SPI2_D1passive
Y3VSSpassive
Y4VSSpassive
Y5OLDI0_A4Ppassive
Y6VSSpassive
Y7OLDI0_CLK1Npassive
Y8OLDI0_A7Ppassive
Y9OLDI0_A6Ppassive
A10MCU_GPIO0_18/MCU_I2C0_SDApassive
A11~{TRST}passive
A12MCU_GPIO0_21/MCU_RESETSTATzpassive
A13GPIO1_20/UART0_RXD/ECAP1_IN_APWM_OUT/SPI2_D0/EHRPWM2_Apassive
A14GPIO1_19/SPI0_D1/CP_GEMAC_CPTS0_HW2TSPUSH/EHRPWM_TZn_IN0passive
A15GPIO1_25/MCAN0/UART5/TIMER/SYNC3/UART1/EQEP2/PR0/MCASP2/EHRPWMpassive
A16GPIO1_29/I2C1_SDA/UART1_TXD/TIMER_IO1/SPI2_CLK/EHRPWM0_SYNCO/~{EHRPWM2_B}/MMC2_SDWPpassive
A17GPIO1_28/I2C1_SCL/UART1_RXD/TIMER_IO0/SPI2_CS1/EHRPWM0_SYNCI/EHRPWM2_A/MMC2_SDCDpassive
A18GPIO1_9/MCASP0_AXR1/SPI2_CS2/ECAP1_IN_APWM_OUT/PR0_UART0_RXD/EHRPWM1_A/EQEP0_Spassive
A19GPIO1_45/MMC1_DAT0/CP_GEMAC_CPTS0_HW2TSPUSH/TIMER_IO3/UART2_CTSn/ECAP2_IN_APWM_OUTpassive
A20GPIO1_46/MMC1_CLK/TIMER_IO4/UART3_RXDpassive
A21VSSpassive
AA1VSSpassive
AA2OLDI0_A0Npassive
AA3OLDI0_A0Ppassive
AA4OLDI0_A4Npassive
AA5OLDI0_A5Ppassive
AA6OLDI0_A5Npassive
AA7OLDI0_CLK1Ppassive
AA8OLDI0_A7Npassive
AA9VSSpassive
B10EMU1passive
B11TMSpassive
B12MCU_GPIO0_23/WKUP_CLKOUT0passive
B13GPIO1_24/MCAN0/UART5/TIMER/SYNC2/UART1/EQEP2/PR0/MCASP2/EHRPWMpassive
B14GPIO1_22/UART0/SPI0/I2C3/UART2/TIMER/AUDIO/PR0/MCASP2/MMC2passive
B15GPIO1_49/MMC1_SDWP/UART6_TXD/TIMER_IO7/UART3_CTSnpassive
B16GPIO1_31/EXTINTnpassive
B17GPIO1_8/MCASP0/SPI2/UART1/UART6/PR0/ECAP2/EQEP0passive
B18GPIO1_7/MCASP0/SPI2/UART1/UART6/PR0/ECAP1/EQEP0passive
B19GPIO1_44/MMC1_DAT1/CP_GEMAC_CPTS0_HW1TSPUSH/TIMER_IO2/UART2_RTSn/ECAP1_IN_APWM_OUTpassive
B20GPIO1_43/MMC1_DAT2/CP_GEMAC_CPTS0_TS_SYNC/TIMER_IO1/UART2_TXDpassive
B21GPIO0_68/MMC2_DAT0/MCASP1_AXR0passive
C10TCKpassive
C11GPIO1_15/SPI0_CS0/EHRPWM0_A/PR0_ECAP0_SYNC_INpassive
C12GPIO1_18/SPI0_D0/CP_GEMAC_CPTS0_HW1TSPUSH/~{EHRPWM1_B}passive
C13GPIO1_23/UART0/SPI0/I2C3/UART2/TIMER/AUDIO/PR0/MCASP2/MMC2passive
C14GPIO1_30/SYSCLKOUT0/CLKOUT0/EXT/SYNC1/SPI2/TIMER/CP/ECAP0passive
C15GPIO1_48/MMC1_SDCD/UART6_RXD/TIMER_IO6/UART3_RTSnpassive
C16GPIO1_12/MCASP0_AFSX/SPI2_CS3/AUDIO_EXT_REFCLK1/~{EQEP1_B}passive
C17GPIO1_11/MCASP0_ACLKX/SPI2_CS1/ECAP2_IN_APWM_OUT/EQEP1_Apassive
C18GPIO1_47/MMC1_CMD/TIMER_IO5/UART3_TXDpassive
C19GPIO1_42/MMC1_DAT3/CP_GEMAC_CPTS0_TS_COMP/TIMER_IO0/UART2_RXDpassive
C20GPIO0_72/MMC2_SDWP/MCASP1_AFSX/UART4_TXDpassive
C21GPIO0_70/MMC2_CMD/MCASP1_AFSR/MCASP1_AXR4/UART6_TXDpassive
D10TDIpassive
D11VSSpassive
D12GPIO1_17/SPI0_CLK/CP_GEMAC_CPTS0_TS_SYNC/EHRPWM1_Apassive
D13GPIO1_16/SPI0_CS1/CP_GEMAC_CPTS0_TS_COMP/~{EHRPWM0_B}/ECAP0_IN_APWM_OUT/EHRPWM_TZn_IN5passive
D14GPIO1_27/I2C0/PR0/SPI2/TIMER/UART1/EQEP2/EHRPWM/ECAP2passive
D15GPIO1_13/MCASP0_AFSR/SPI2_CS0/UART1_RXD/EHRPWM0_A/EQEP1_Spassive
D16GPIO1_14/MCASP0_ACLKR/SPI2_CLK/UART1_TXD/~{EHRPWM0_B}/EQEP1_Ipassive
D17GPIO1_50/USB0_DRVVBUSpassive
D18GPIO1_10/MCASP0_AXR0/PR0_ECAP0_IN_APWM_OUT/AUDIO_EXT_REFCLK0/PR0_UART0_TXD/~{EHRPWM1_B}/EQEP0_Ipassive
D19VSSpassive
D20GPIO0_71/MMC2_SDCD/MCASP1_ACLKX/UART4_RXDpassive
D21GPIO0_67/MMC2_DAT1/MCASP1_AXR1passive
E10TDOpassive
E11GPIO1_21/UART0_TXD/ECAP2_IN_APWM_OUT/SPI2_D1/~{EHRPWM2_B}passive
E12GPIO1_26/OBSCLK0/I2C0/PR0/SYNC0/UART1/EQEP2/EHRPWM/ECAP1/SPI2passive
E13~{POR_OUT}passive
E14~{RESETSTAT}passive
E15~{RESET_REQ}passive
E16GPIO1_51/USB1_DRVVBUSpassive
E17GPIO0_13/OSPI0_CSn2/SPI1_CS1/OSPI0_RESET_OUT1/MCASP1_AFSR/MCASP1_AXR2/UART5_RXDpassive
E18GPIO0_14/OSPI0_CSn3/OSPI0_RESET_OUT0/OSPI0_ECC_FAIL/MCASP1_ACLKR/MCASP1_AXR3/UART5_TXDpassive
E19GPIO0_66/MMC2_DAT2/MCASP1_AXR2/UART5_TXDpassive
E20GPIO0_65/MMC2_DAT3/MCASP1_AXR3/UART5_RXDpassive
E21GPIO0_69/MMC2_CLK/MCASP1_ACLKR/MCASP1_AXR5/UART6_RXDpassive
F10VDDSHV_MCUpassive
F11VSSpassive
F12VDDSHV0passive
F13VSSpassive
F14VDDSHV5passive
F15VSSpassive
F16VDDA_TEMP1passive
F17GPIO0_12/OSPI0_CSn1passive
F18GPIO0_3/OSPI0_D0passive
F19GPIO0_11/OSPI0_CSn0passive
F20GPIO0_6/OSPI0_D3passive
F21GPIO0_5/OSPI0_D2passive
G10VDDSHV_MCUpassive
G11CAP_VDDS_MCUpassive
G12CAP_VDDS0passive
G13VDDSHV0passive
G14VDDSHV5passive
G15CAP_VDDS5passive
G16VSSpassive
G17GPIO0_4/OSPI0_D1passive
G18GPIO0_1/OSPI0_LBCLKO/UART5_RTSnpassive
G19GPIO0_0/OSPI0_CLKpassive
G20GPIO0_9/OSPI0_D6/SPI1_D0/MCASP1_ACLKX/UART6_RTSnpassive
G21GPIO0_7/OSPI0_D4/SPI1_CS0/MCASP1_AXR1/UART6_RXDpassive
H10VDDA_MCUpassive
H11VDDR_COREpassive
H12VDD_COREpassive
H13VSSpassive
H14VDD_COREpassive
H15VDDSHV6passive
H16VDDSHV6passive
H17GPIO0_42/GPMC0/PR0/MCASP2/TRCpassive
H18GPIO0_43/GPMC0/I2C2/MCASP1/UART4/PR0/TRCpassive
H19GPIO0_44/GPMC0_CSn3/I2C2_SDA/GPMC0_A20/UART4_TXD/MCASP1_AXR5/TRC_DATA18/MCASP1_ACLKRpassive
H20GPIO0_2/OSPI0_DQS/UART5_CTSnpassive
H21GPIO0_8/OSPI0_D5/SPI1_CLK/MCASP1_AXR0/UART6_TXDpassive
J10VSSpassive
J11VDD_COREpassive
J12VSSpassive
J13VDD_COREpassive
J14VSSpassive
J15CAP_VDDS6passive
J16VSSpassive
J17GPIO0_34/GPMC0_WEn/MCASP1_AXR0/PR0_PRU0_GPO11/PR0_PRU0_GPI11/TRC_DATA9passive
J18GPIO0_41/GPMC0_CSn0/MCASP2_AXR14/PR0_PRU0_GPO17/PR0_PRU0_GPI17/TRC_DATA15passive
J19GPIO0_40/GPMC0/PR0/MCASP2/TRC/EQEP2passive
J20GPIO0_39/GPMC0_WPn/AUDIO_EXT_REFCLK1/GPMC0_A22/UART6_TXD/PR0_PRU0_GPO15/PR0_PRU0_GPI15/TRC_DATA13passive
J21GPIO0_10/OSPI0_D7/SPI1_D1/MCASP1_AFSX/UART6_CTSnpassive
K10VDD_COREpassive
K11VMON_3P3_SOCpassive
K12VDDA_PLL2passive
K13VSSpassive
K14VDD_COREpassive
K15VDDSHV1passive
K16VDDSHV1passive
K17~{GPIO0_35}/~{GPMC0_BE0n_CLE}/MCASP1_ACLKX/PR0_PRU0_GPO12/PR0_PRU0_GPI12/TRC_DATA10passive
K18~{GPIO0_36}/~{GPMC0_BE1n}/MCASP2_AXR12/PR0_PRU0_GPO13/PR0_PRU0_GPI13/TRC_DATA11passive
K19GPIO0_15/GPMC0_AD0/PR0_PRU1_GPO8/PR0_PRU1_GPI8/MCASP2_AXR4/PR0_PRU0_GPO0/PR0_PRU0_GPI0/TRC_CLKpassive
K20GPIO0_32/GPMC0_ADVn_ALE/MCASP1_AXR2/PR0_PRU0_GPO9/PR0_PRU0_GPI9/TRC_DATA7passive
K21GPIO0_33/GPMC0_OEn_REn/MCASP1_AXR1/PR0_PRU0_GPO10/PR0_PRU0_GPI10/TRC_DATA8passive
L10VSSpassive
L11VDD_COREpassive
L12VSSpassive
L13VDD_COREpassive
L14VSSpassive
L15CAP_VDDS1passive
L16VSSpassive
L17GPIO0_20/GPMC0_AD5/PR0_PRU1_GPO13/PR0_PRU1_GPI13/MCASP2_AXR9/PR0_PRU0_GPO5/PR0_PRU0_GPI5/TRC_DATA3passive
L18GPIO0_21/GPMC0_AD6/PR0_PRU1_GPO14/PR0_PRU1_GPI14/MCASP2_AXR10/PR0_PRU0_GPO6/PR0_PRU0_GPI6/TRC_DATA4passive
L19GPIO0_16/GPMC0_AD1/PR0_PRU1_GPO9/PR0_PRU1_GPI9/MCASP2_AXR5/PR0_PRU0_GPO1/PR0_PRU0_GPI1/TRC_CTLpassive
L20GPIO0_17/GPMC0_AD2/PR0_PRU1_GPO10/PR0_PRU1_GPI10/MCASP2_AXR6/PR0_PRU0_GPO2/PR0_PRU0_GPI2/TRC_DATA0passive
L21GPIO0_18/GPMC0_AD3/PR0_PRU1_GPO11/PR0_PRU1_GPI11/MCASP2_AXR7/PR0_PRU0_GPO3/PR0_PRU0_GPI3/TRC_DATA1passive
M10VDDR_COREpassive
M11VSSpassive
M12VDD_COREpassive
M13VDDR_COREpassive
M14VDD_COREpassive
M15CAP_VDDS3passive
M16VSSpassive
M17GPIO0_25/GPMC0_AD10/VOUT0_DATA18/UART3_RXD/MCASP2_AXR2/PR0_PRU1_GPO2/PR0_PRU1_GPI2/OBSCLK0passive
M18VSSpassive
M19GPIO0_31/GPMC0_CLK/MCASP1_AXR3/GPMC0_FCLK_MUX/PR0_PRU0_GPO8/PR0_PRU0_GPI8/TRC_DATA6passive
M20GPIO0_22/GPMC0_AD7/PR0_PRU1_GPO15/PR0_PRU1_GPI15/MCASP2_AXR11/PR0_PRU0_GPO7/PR0_PRU0_GPI7/TRC_DATA5passive
M21GPIO0_19/GPMC0_AD4/PR0_PRU1_GPO12/PR0_PRU1_GPI12/MCASP2_AXR8/PR0_PRU0_GPO4/PR0_PRU0_GPI4/TRC_DATA2passive
N10VDDA_PLL0passive
N11VDD_COREpassive
N12VSSpassive
N13VDD_COREpassive
N14VSSpassive
N15VDDSHV3passive
N16VDDSHV3passive
N17GPIO0_27/GPMC0_AD12/VOUT0_DATA20/UART4_RXD/MCASP2_AFSX/PR0_PRU0_GPO0/PR0_PRU0_GPI0/TRC_DATA22passive
N18GPIO0_26/GPMC0_AD11/VOUT0_DATA19/UART3_TXD/MCASP2_AXR3/PR0_PRU1_GPO3/PR0_PRU1_GPI3/TRC_DATA23passive
N19GPIO0_28/GPMC0_AD13/VOUT0_DATA21/UART4_TXD/MCASP2_ACLKX/PR0_PRU0_GPO1/PR0_PRU0_GPI1/TRC_DATA21passive
N20GPIO0_23/GPMC0_AD8/VOUT0_DATA16/UART2_RXD/MCASP2_AXR0/PR0_PRU1_GPO0/PR0_PRU1_GPI0passive
N21GPIO0_24/GPMC0_AD9/VOUT0_DATA17/UART2_TXD/MCASP2_AXR1/PR0_PRU1_GPO1/PR0_PRU1_GPI1passive
P10VSSpassive
P11VDDA_CORE_USBpassive
P12VDDA_CORE_CSIRX0passive
P13VSSpassive
P14VDDA_PLL1passive
P15VSSpassive
P16VSSpassive
P17GPIO0_38/GPMC0_WAIT1/VOUT0_EXTPCLKIN/GPMC0_A21/UART6_RXD/EQEP2_Ipassive
P18GPIO0_46/VOUT0_DATA1/GPMC0_A1/PR0_PRU1_GPO1/PR0_PRU1_GPI1/UART2_TXD/PR0_PRU0_GPO9/PR0_PRU0_GPI9passive
P19GPIO0_29/GPMC0/VOUT0/UART5/MCASP2/PR0/TRC/UART2passive
P20GPIO0_30/GPMC0/VOUT0/UART5/MCASP2/PR0/TRC/UART2passive
P21GPIO0_37/GPMC0_WAIT0/MCASP1_AFSX/PR0_PRU0_GPO14/PR0_PRU0_GPI14/TRC_DATA12passive
R10VDDA_3P3_USBpassive
R11VDDA_1P8_USBpassive
R12VDDA_1P8_CSIRX0passive
R13CAP_VDDS2passive
R14VDDSHV2passive
R15VDDSHV2passive
R16VSSpassive
R17GPIO0_54/VOUT0_DATA9/GPMC0_A9/PR0_PRU1_GPO8/PR0_PRU1_GPI8/UART6_TXD/PR0_PRU0_GPO16/PR0_PRU0_GPI16passive
R18GPIO0_47/VOUT0_DATA2/GPMC0_A2/PR0_PRU1_GPO2/PR0_PRU1_GPI2/UART3_RXD/PR0_PRU0_GPO10/PR0_PRU0_GPI10passive
R19GPIO0_48/VOUT0_DATA3/GPMC0_A3/PR0_PRU1_GPO3/PR0_PRU1_GPI3/UART3_TXD/PR0_PRU0_GPO11/PR0_PRU0_GPI11passive
R20GPIO0_49/VOUT0_DATA4/GPMC0_A4/PR0_PRU1_GPO4/PR0_PRU1_GPI4/UART4_RXD/PR0_PRU0_GPO12/PR0_PRU0_GPI12passive
R21GPIO0_45/VOUT0_DATA0/GPMC0_A0/PR0_PRU1_GPO0/PR0_PRU1_GPI0/UART2_RXD/PR0_PRU0_GPO8/PR0_PRU0_GPI8passive
T10VSSpassive
T11CSI0_RXRCALIBpassive
T12VSSpassive
T15VSSpassive
T16GPIO0_63/VOUT0/GPMC0/PR0/UART2passive
T17GPIO0_62/VOUT0_DE/GPMC0_A17/PR0_PRU1_GPO17/PR0_PRU1_GPI17/UART3_CTSn/PR0_PRU0_GPO7/PR0_PRU0_GPI7passive
T18GPIO0_55/VOUT0_DATA10/GPMC0_A10/PR0_PRU1_GPO9/PR0_PRU1_GPI9/UART6_RTSn/PR0_PRU0_GPO0/PR0_PRU0_GPI0passive
T19GPIO0_52/VOUT0_DATA7/GPMC0_A7/PR0_PRU1_GPO7/PR0_PRU1_GPI7/UART5_TXD/PR0_PRU0_GPO15/PR0_PRU0_GPI15passive
T20GPIO0_50/VOUT0_DATA5/GPMC0_A5/PR0_PRU1_GPO5/PR0_PRU1_GPI5/UART4_TXD/PR0_PRU0_GPO13/PR0_PRU0_GPI13passive
T21GPIO0_51/VOUT0_DATA6/GPMC0_A6/PR0_PRU1_GPO6/PR0_PRU1_GPI6/UART5_RXD/PR0_PRU0_GPO14/PR0_PRU0_GPI14passive
U10VSSpassive
U11CSI0_RXP2passive
U12CSI0_RXN2passive
U13VSSpassive
U14GPIO0_75/RGMII1_TD0/RMII1_TXD0passive
U15GPIO0_90/RGMII2_TD1/RMII2_TXD1/MCASP2_ACLKR/PR0_PRU1_GPO3/PR0_PRU1_GPI3/MCASP2_AXR8passive
U16GPIO0_85/MDIO0_MDIOpassive
U17GPIO0_64/VOUT0/GPMC0/PR0/UART2passive
U18GPIO0_59/VOUT0_DATA14/GPMC0_A14/PR0_PRU1_GPO13/PR0_PRU1_GPI13/UART4_RTSn/PR0_PRU0_GPO4/PR0_PRU0_GPI4passive
U19GPIO0_57/VOUT0_DATA12/GPMC0_A12/PR0_PRU1_GPO11/PR0_PRU1_GPI11/UART5_RTSn/PR0_PRU0_GPO2/PR0_PRU0_GPI2passive
U20GPIO0_56/VOUT0_DATA11/GPMC0_A11/PR0_PRU1_GPO10/PR0_PRU1_GPI10/UART6_CTSn/PR0_PRU0_GPO1/PR0_PRU0_GPI1passive
U21GPIO0_53/VOUT0_DATA8/GPMC0_A8/PR0_PRU1_GPO16/PR0_PRU1_GPI16/UART6_RXD/PR0_PRU0_GPO17/PR0_PRU0_GPI17passive
V10USB0_VBUSpassive
V11VSSpassive
V12CSI0_RXP1passive
V13CSI0_RXN1passive
V14VSSpassive
V15GPIO0_73/RGMII1_TX_CTL/RMII1_TX_ENpassive
V16GPIO1_0/RGMII2/MCASP2/PR0/EQEP2passive
V17GPIO0_86/MDIO0_MDCpassive
V18GPIO1_2/RGMII2_RXC/RMII2_REF_CLK/MCASP2_AXR1/PR0_PRU0_GPO1/PR0_PRU0_GPI1/PR0_ECAP0_SYNC_INpassive
V19VSSpassive
V20GPIO0_60/VOUT0_DATA15/GPMC0_A15/PR0_PRU1_GPO14/PR0_PRU1_GPI14/UART4_CTSn/PR0_PRU0_GPO5/PR0_PRU0_GPI5passive
V21GPIO0_58/VOUT0_DATA13/GPMC0_A13/PR0_PRU1_GPO12/PR0_PRU1_GPI12/UART5_CTSn/PR0_PRU0_GPO3/PR0_PRU0_GPI3passive
W10VSSpassive
W11CSI0_RXP3passive
W12CSI0_RXN3passive
W13VSSpassive
W14GPIO0_79/RGMII1_RX_CTL/RMII1_RX_ERpassive
W15GPIO0_81/RGMII1_RD0/RMII1_RXD0passive
W16GPIO0_74/RGMII1_TXC/RMII1_CRS_DVpassive
W17GPIO0_91/RGMII2_TD2/MCASP2_AFSX/PR0_PRU1_GPO4/PR0_PRU1_GPI4/PR0_ECAP0_IN_APWM_OUT/EQEP2_Ipassive
W18GPIO1_3/RGMII2_RD0/RMII2_RXD0/MCASP2_AXR2/PR0_PRU0_GPO2/PR0_PRU0_GPI2/PR0_UART0_RTSnpassive
W19GPIO1_1/RGMII2_RX_CTL/RMII2_RX_ER/MCASP2_AXR3/PR0_PRU0_GPO0/PR0_PRU0_GPI0passive
W20GPIO1_6/RGMII2_RD3/AUDIO_EXT_REFCLK0/PR0_PRU0_GPO16/PR0_PRU0_GPI16/PR0_UART0_TXD/~{EQEP2_B}passive
W21GPIO0_61/VOUT0_HSYNC/GPMC0_A16/PR0_PRU1_GPO15/PR0_PRU1_GPI15/UART3_RTSn/PR0_PRU0_GPO6/PR0_PRU0_GPI6passive
Y10USB0_DPpassive
Y11VSSpassive
Y12CSI0_RXP0passive
Y13CSI0_RXN0passive
Y14VSSpassive
Y15GPIO0_84/RGMII1_RD3passive
Y16GPIO0_82/RGMII1_RD1/RMII1_RXD1passive
Y17GPIO0_77/RGMII1_TD2/PR0_UART0_RXDpassive
Y18GPIO0_88/RGMII2_TXC/RMII2_CRS_DV/MCASP2_AXR5/PR0_PRU1_GPO1/PR0_PRU1_GPI1passive
Y19GPIO1_5/RGMII2_RD2/MCASP2_AXR0/PR0_PRU0_GPO4/PR0_PRU0_GPI4/PR0_UART0_RXD/EQEP2_Apassive
Y20GPIO1_4/RGMII2_RD1/RMII2_RXD1/MCASP2_AFSR/PR0_PRU0_GPO3/PR0_PRU0_GPI3/MCASP2_AXR7passive
Y21GPIO0_87/RGMII2_TX_CTL/RMII2_TX_EN/MCASP2_AXR4/PR0_PRU1_GPO0/PR0_PRU1_GPI0passive
AA10OLDI0_A6Npassive
AA11USB0_DMpassive
AA12VSSpassive
AA13CSI0_RXCLKPpassive
AA14CSI0_RXCLKNpassive
AA15VSSpassive
AA16GPIO0_80/RGMII1_RXC/RMII1_REF_CLK/PR0_UART0_CTSnpassive
AA17GPIO0_83/RGMII1_RD2/PR0_UART0_RTSnpassive
AA18GPIO0_78/RGMII1_TD3/PR0_UART0_TXDpassive
AA19GPIO0_76/RGMII1_TD1/RMII1_TXD1passive
AA20GPIO0_89/RGMII2_TD0/RMII2_TXD0/MCASP2_AXR6/PR0_PRU1_GPO2/PR0_PRU1_GPI2passive
AA21VSSpassive

Provenance

Credit
Celestial Altium Library by Issus and contributors (https://github.com/issus/altium-library)
Licence
LicenseRef-Celestial-Altium
Link method
none
Cross-check
not confirmed