Components
48 matching
Each one is a symbol, its recommended footprint and its 3D package model, linked by KiCad's own references and cross-checked pin by pin.
TB5R2DW
Interface
Quad differential PECL reciver
- Pins
- 16
- Pads
- 16
- SMD
- 11.9×10.8
PEEL22CV10AP
Logic_Programmable
Not in Production, CMOS Programmable Electrically Erasable Logic Device, DIP-24
- Pins
- 24
- Pads
- 24
- THT
- 9.7×31.0
MC100EPT22DT
Interface
3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Translator, TSSOP-8
- Pins
- 8
- Pads
- 8
- SMD
- 5.9×3.6
TB5D1MDW
Interface
Quad differential PECL driver
- Pins
- 16
- Pads
- 16
- SMD
- 11.9×10.8
MC100LVELT22DT
Interface
3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Translator, TSSOP-8
- Pins
- 8
- Pads
- 8
- SMD
- 5.9×3.6
TB5R1DW
Interface
Quad differential PECL reciver
- Pins
- 16
- Pads
- 16
- SMD
- 11.9×10.8
EPM570T144
CPLD_Altera
Altera MAX2 CPLD with 570 LE
- Pins
- 144
- Pads
- 144
- SMD
- 23.3×23.3
TB5D2HDW
Interface
Quad differential PECL driver
- Pins
- 16
- Pads
- 16
- SMD
- 11.9×10.8
TB5D2H
Interface
Quad differential PECL driver
- Pins
- 16
- Pads
- 16
- SMD
- 7.4×10.4
EPM570T100
CPLD_Altera
Altera MAX2 CPLD with 570 LE
- Pins
- 100
- Pads
- 100
- SMD
- 17.5×17.5
TB5R1D
Interface
Quad differential PECL reciver
- Pins
- 16
- Pads
- 16
- SMD
- 7.4×10.4
LCMXO2-640xx-xTG100
gekkio-Gekkio_FPGA_Lattice
MachXO2 FPGA, 640 LUT, TQFP-100
- Pins
- 100
- Pads
- 100
- SMD
- 17.3×17.3
TB5R2D
Interface
Quad differential PECL reciver
- Pins
- 16
- Pads
- 16
- SMD
- 7.4×10.4
TB5D1MD
Interface
Quad differential PECL driver
- Pins
- 16
- Pads
- 16
- SMD
- 7.4×10.4
MC100LVELT22D
Interface
3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Translator, SOIC-8
- Pins
- 8
- Pads
- 8
- SMD
- 7.4×5.4
MC100EPT22D
Interface
3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Translator, SOIC-8
- Pins
- 8
- Pads
- 8
- SMD
- 7.4×5.4
EP310
CPLD_Altera
EPLD, 8 Macrocell, DIP-20
- Pins
- 20
- Pads
- 20
- THT
- 9.7×25.9
LCMXO2-1200xx-xTG100
gekkio-Gekkio_FPGA_Lattice
MachXO2 FPGA, 1200 LUT, TQFP-100
- Pins
- 100
- Pads
- 100
- SMD
- 17.3×17.3
LCMXO2-256xx-xTG100
gekkio-Gekkio_FPGA_Lattice
MachXO2 FPGA, 256 LUT, TQFP-100
- Pins
- 100
- Pads
- 100
- SMD
- 17.3×17.3
LCMXO2-2000xx-xTG144
gekkio-Gekkio_FPGA_Lattice
MachXO2 FPGA, 2000 LUT, TQFP-144
- Pins
- 144
- Pads
- 144
- SMD
- 23.3×23.3
EP300
CPLD_Altera
EPLD, DIP-20
- Pins
- 20
- Pads
- 20
- THT
- 9.7×25.9
LC4032ZE-xxTN48
gekkio-Gekkio_CPLD_Lattice
1.8 V In-System Programmable Ultra Low Power PLD, 32 macrocells, TQFP-48
- Pins
- 48
- Pads
- 48
- SMD
- 10.3×10.3
LCMXO2-7000xx-xTG144
gekkio-Gekkio_FPGA_Lattice
MachXO2 FPGA, 7000 LUT, TQFP-144
- Pins
- 144
- Pads
- 144
- SMD
- 23.3×23.3
PEEL22CV10AS
Logic_Programmable
Not in Production, CMOS Programmable Electrically Erasable Logic Device, SOIC-24W
- Pins
- 24
- Pads
- 24
- SMD
- 11.9×15.9
EPM1270T144
CPLD_Altera
Altera MAX2 CPLD with 1270 LE
- Pins
- 144
- Pads
- 144
- SMD
- 23.3×23.3
LCMXO2-2000xx-xTG100
gekkio-Gekkio_FPGA_Lattice
MachXO2 FPGA, 2000 LUT, TQFP-100
- Pins
- 100
- Pads
- 100
- SMD
- 17.3×17.3
LC4256ZE-xxTN100
gekkio-Gekkio_CPLD_Lattice
1.8 V In-System Programmable Ultra Low Power PLD, 256 macrocells, TQFP-100
- Pins
- 100
- Pads
- 100
- SMD
- 17.3×17.3
LC4128ZE-xxTN100
gekkio-Gekkio_CPLD_Lattice
1.8 V In-System Programmable Ultra Low Power PLD, 256 macrocells, TQFP-100
- Pins
- 100
- Pads
- 100
- SMD
- 17.3×17.3
LCMXO2-4000xx-xTG144
gekkio-Gekkio_FPGA_Lattice
MachXO2 FPGA, 4000 LUT, TQFP-144
- Pins
- 144
- Pads
- 144
- SMD
- 23.3×23.3
LC4064ZE-xxTN48
gekkio-Gekkio_CPLD_Lattice
1.8 V In-System Programmable Ultra Low Power PLD, 64 macrocells, TQFP-48
- Pins
- 48
- Pads
- 48
- SMD
- 10.3×10.3
S5933_PQ160
Interface
PCI 2.1 Compliant Master/Slave Device, PQFP-160
- Pins
- 158
- Pads
- 160
- SMD
- 32.5×32.5
LC4128ZE-xxTN144
gekkio-Gekkio_CPLD_Lattice
1.8 V In-System Programmable Ultra Low Power PLD, 128 macrocells, TQFP-144
- Pins
- 144
- Pads
- 144
- SMD
- 23.3×23.3
LC4256ZE-xxTN144
gekkio-Gekkio_CPLD_Lattice
1.8 V In-System Programmable Ultra Low Power PLD, 256 macrocells, TQFP-144
- Pins
- 144
- Pads
- 144
- SMD
- 23.3×23.3
LFXP2-5E-7TN144
FPGA_Lattice
FPGA, 5000 LUTs, 1.2V, TQFP-144
- Pins
- 144
- Pads
- 144
- SMD
- 23.3×23.3
LFXP2-5E-5TN144
FPGA_Lattice
FPGA, 5000 LUTs, 1.2V, TQFP-144
- Pins
- 144
- Pads
- 144
- SMD
- 23.3×23.3
PAL20R8xx-P
Logic_Programmable
Programmable Array Logic (PAL), 20 array inputs (12 dedicated inputs), 8 registered outputs (active-low), DIP-24
- Pins
- 24
- Pads
- 24
- THT
- 9.7×31.0
ATF16V8Bxx-xxPU
Logic_Programmable
High-performance EE PLD, PAL Device Emulation / PAL Replacement, DIP-20
- Pins
- 20
- Pads
- 20
- THT
- 9.7×25.9
EPM240T100
CPLD_Altera
Altera MAX2 CPLD with 240 LE
- Pins
- 100
- Pads
- 100
- SMD
- 17.5×17.5
LFXP2-5E-6TN144
FPGA_Lattice
FPGA, 5000 LUTs, 1.2V, TQFP-144
- Pins
- 144
- Pads
- 144
- SMD
- 23.3×23.3
LC4064ZE-xxTN100
gekkio-Gekkio_CPLD_Lattice
1.8 V In-System Programmable Ultra Low Power PLD, 256 macrocells, TQFP-100
- Pins
- 100
- Pads
- 100
- SMD
- 17.3×17.3
PAL20L8
Logic_Programmable
Programmable Array Logic (PAL), Active-Low Combinatorial, DIP-24
- Pins
- 24
- Pads
- 24
- THT
- 9.7×31.0
XC95144XL-TQ144
CPLD_Xilinx
CPLD, 144 Macrocells, 3200 Usable Gates
- Pins
- 144
- Pads
- 144
- SMD
- 23.3×23.3
PCI9030-PQFP176
Interface
PCI SMARTarget I/O Accelerator
- Pins
- 176
- Pads
- 176
- SMD
- 27.4×27.4
DSPIC33EP256MU810-xPT
DSP_Microchip_DSPIC33
High-Performance, 16-bit Digital Signal Controller, 40MIPS, 256k Flash, 30k SRAM, TQFP-100
- Pins
- 100
- Pads
- 100
- SMD
- 17.3×17.3
XC9572XL-xxTQx100
CPLD_Xilinx
CPLD, 72 Macrocells, 1600 Usable Gates, LQFP-100 (Xilinx TQ100)
- Pins
- 100
- Pads
- 100
- SMD
- 17.5×17.5
EPM570ZM144
CPLD_Altera
Altera Zero-Power MAX2 CPLD with 570 LE
- Pins
- 144
- Pads
- 144
- SMD
- 9.0×9.0
XC95144XL-TQ100
CPLD_Xilinx
CPLD, 144 Macrocells, 3200 Usable Gates
- Pins
- 100
- Pads
- 100
- SMD
- 17.3×17.3
CYBL10563-56LQXQ
MCU_Cypress
56-QFN, 48-MHz ARM® Cortex®-M0, 128KB Flash, 16kB SRAM, BLE 4.1, CAP-SENSE W/ GESTURES, 2 SCB, 4 TCPWM, I2S, 1 PWM , LCD, 1MSPS 12-BIT SAR
- Pins
- 57
- Pads
- 57
- SMD
- 8.3×8.3
