Reference schematic

Stm32f103 SIM7600

Vtechcode-stm32f103_sim7600-stm32f103_sim7600-schematic

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Vtechcode-stm32f103_sim7600-stm32f103_sim7600-schematic

Take the project archive: a schematic is a root sheet plus every sub-sheet beside it, and the root alone opens with its hierarchy missing. The archive is zstd-compressed (tar.zst).

1Sheets
66Placed parts
21Net labels
KiCad 8File format

Bill of materials

66 distinct parts

61 resolve to something in the catalog — click through to the component.

RefValueSymbolQty
C131uFDevice:C
C14100uFDevice:C_Polarized_Small_US
C15100uFDevice:C_Polarized_Small_US
C16100nFDevice:C_Small
C17100nFDevice:C_Small
C220.1uFDevice:C_Small
C230.1uFDevice:C_Small
C240.1uFDevice:C_Small
C2522pFDevice:C_Small
C2622pFDevice:C_Small
C2722pFDevice:C_Small
C28C_SmallDevice:C_Small
C29C_SmallDevice:C_Small
C30C_SmallDevice:C_Small
C31C_SmallDevice:C_Small
C32C_SmallDevice:C_Small
C3333pFDevice:C_Small
D10ESD5ZxxDiode:ESD5Zxx
D11ESD5ZxxDiode:ESD5Zxx
D12LEDDevice:LED
D13ESD9B3.3ST5GDiode:ESD9B3.3ST5G
D14ESD9B3.3ST5GDiode:ESD9B3.3ST5G
D3ESD9B3.3ST5GDiode:ESD9B3.3ST5G
D4D_TVSDevice:D_TVS
D5LEDDevice:LED
D6ESD9B3.3ST5GDiode:ESD9B3.3ST5G
D8ESD5ZxxDiode:ESD5Zxx
D9ESD5ZxxDiode:ESD5Zxx
FB2FerriteBead_SmallDevice:FerriteBead_Small
J2SIM7100-6-1-15-00-A_REVC2SIM7100:SIM7100-6-1-15-00-A_REVC2
J3CONUFL001-SMD-TUFL CONNECTOR:CONUFL001-SMD-T
J4CONUFL001-SMD-TUFL CONNECTOR:CONUFL001-SMD-T
J5CONUFL001-SMD-TUFL CONNECTOR:CONUFL001-SMD-T
L1LDevice:L
L2LDevice:L
L347nHDevice:L
Q1NPNSimulation_SPICE:NPN
Q2NPNSimulation_SPICE:NPN
Q3NPNSimulation_SPICE:NPN
R1047KDevice:R
Show the other 26
R1147KDevice:R
R1247KDevice:R
R1347KDevice:R
R1447KDevice:R
R1547KDevice:R
R1622RDevice:R
R1722RDevice:R
R1822RDevice:R
R194.7KDevice:R
R2047KDevice:R
R2147KDevice:R
R220RDevice:R_Small
R230RDevice:R_Small
R240RDevice:R_Small
R250RDevice:R_Small
R2610RDevice:R_Small
R2747KDevice:R
R44.7KDevice:R
R547KDevice:R
R61.5KDevice:R
R74.7KDevice:R
R847KDevice:R
R947KDevice:R
SW3SW_PushSwitch:SW_Push
U2SIM7600ESIM7600E:SIM7600E
U4TXB0108RGYLogic_LevelTranslator:TXB0108RGY

Provenance

Commit
unknown
Licence
CC-BY-4.0

How it is used

Trace's agent reads this design as context — what parts a board like this carries, how they are grouped across sheets, what a plausible layer stack and board size look like for the job. It is not copied. The licence above is permissive, and it, the repository and the commit are recorded so the origin of anything derived from it is always answerable.