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Reference layout

Esdi Emulator

cwsimmons-esdi_emulator-esdi_emulator-layout

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cwsimmons-esdi_emulator-esdi_emulator-layout

The project archive carries the board, its project file and the upstream licence. The archive is zstd-compressed (tar.zst).

50Placed parts
191Nets
2Copper layers
98.04 × 59.7 mmBoard size
yesRouted
KiCad 8File format

Bill of materials

50 distinct parts

46 resolve to something in the catalog — click through to the footprint.

RefValueFootprintQty
C11uCapacitor_SMD:C_1206_3216Metric
C10CCapacitor_SMD:C_0402_1005Metric
C11CCapacitor_SMD:C_0402_1005Metric
C12CCapacitor_SMD:C_0402_1005Metric
C13CCapacitor_SMD:C_0402_1005Metric
C14CCapacitor_SMD:C_0402_1005Metric
C15CCapacitor_SMD:C_0402_1005Metric
C16CCapacitor_SMD:C_0402_1005Metric
C17CCapacitor_SMD:C_0402_1005Metric
C23300pCapacitor_SMD:C_1206_3216Metric
C31uCapacitor_SMD:C_1206_3216Metric
C410uCapacitor_SMD:C_1206_3216Metric
C5CCapacitor_SMD:C_0402_1005Metric
C6CCapacitor_SMD:C_0402_1005Metric
C7CCapacitor_SMD:C_0402_1005Metric
C8CCapacitor_SMD:C_0402_1005Metric
C9CCapacitor_SMD:C_0402_1005Metric
H1MountingHole_PadMountingHole:MountingHole_2.7mm_M2.5_DIN965_Pad
H2MountingHole_PadMountingHole:MountingHole_2.7mm_M2.5_DIN965_Pad
J1ASP-134604-01custom:CONN_ASP-134604-01_SAI
J2Control Cablecustom:ECON34
J3Data Port Acustom:econ20
J4Data Port BConnector_PinHeader_2.54mm:PinHeader_2x10_P2.54mm_Vertical
JP1EnableConnector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical
JP25VConnector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical
L147ucustom:Inductor_Eaton_SD53
R13p32MResistor_SMD:R_0805_2012Metric
R2866kResistor_SMD:R_0805_2012Metric
R3105Resistor_SMD:R_0805_2012Metric
R4105Resistor_SMD:R_0805_2012Metric
R5150Resistor_SMD:R_0805_2012Metric
R6150Resistor_SMD:R_0805_2012Metric
R7105Resistor_SMD:R_0805_2012Metric
R8105Resistor_SMD:R_0805_2012Metric
RN1R_Network08Resistor_THT:R_Array_SIP9
RN2R_Network08Resistor_THT:R_Array_SIP9
U1MAX17501BxTBPackage_DFN_QFN:TDFN-10-1EP_2x3mm_P0.5mm_EP0.9x2mm
U1074LS06Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
U11~Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
U12~Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
Show the other 10
U13~Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
U14~Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
U2~Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
U3~Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
U4~Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
U5~Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
U674LS06Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
U774LS06Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
U8~Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
U9~Package_SO:SOIC-8_3.9x4.9mm_P1.27mm

Provenance

Commit
unknown
Licence
CC-BY-4.0

How it is used

Trace's agent reads this design as context — what parts a board like this carries, how they are grouped across sheets, what a plausible layer stack and board size look like for the job. It is not copied. The licence above is permissive, and it, the repository and the commit are recorded so the origin of anything derived from it is always answerable.