Footprints

106 footprints matching “L”

Land patterns on their own — 19,830 of them, most never referenced by a symbol in the catalog. Each passed the courtyard and pad checks; 7,626 come with the 3D model they name.

I need

Symbol Footprint 3D model

Footprints on their own, whether or not a symbol uses them.

106 footprints · page 1 of 5

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Linear_HTSSOP-31-38-1EP_4.4x9.7mm_P0.5mm_EP2.74x4.75mm

FP—

Package_SO

Linear HTSSOP, 31 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-tssop/tssop_38_05-08-1865.pdf)

Pads: 32
SMD: 7.1×10.2
Boards: —

Linear_HTSSOP-31-38-1EP_4.4x9.7mm_P0.5mm_EP2.74x4.75mm_ThermalVias

FP—

Package_SO

Linear HTSSOP, 31 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-tssop/tssop_38_05-08-1865.pdf)

Pads: 32
SMD: 7.1×10.2
Boards: —

TI_SO-PowerPAD-8_ThermalVias

FP—

Package_SO

8-pin HTSOP package with 1.27mm pin pitch, compatible with SOIC-8, 3.9x4.9mm² body, exposed pad, thermal vias with large copper area, as proposed in http://www.ti.com/lit/ds/symlink/tps5430.pdf

Pads: 9
SMD: 7.5×5.5
Boards: 103

TSOP-6_1.65x3.05mm_P0.95mm

FP3D

Package_SO

TSOP-6 package (comparable to TSOT-23), https://www.vishay.com/docs/71200/71200.pdf

Pads: 6
SMD: 3.5×3.5
Boards: 69

Texas_HTSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.95x4.9mm_Mask2.4x3.1mm_ThermalVias

FP3D

Package_SO

8-pin HTSOP package with 1.27mm pin pitch, compatible with SOIC-8, 3.9x4.9mm body, exposed pad, thermal vias, http://www.ti.com/lit/ds/symlink/drv8870.pdf

Pads: 9
SMD: 8.4×5.5
Boards: 47

PowerPAK_SO-8_Single

FP—

Package_SO

PowerPAK SO-8 Single (https://www.vishay.com/docs/71655/powerpak.pdf, https://www.vishay.com/docs/72599/72599.pdf)

Pads: 5
SMD: 7.1×5.5
Boards: 41

SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm_ThermalVias

FP3D

Package_SO

SOIC, 8 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ada4898-1_4898-2.pdf#page=29)

Pads: 9
SMD: 7.4×5.4
Boards: 40

Vishay_PowerPAK_1212-8_Single

FP—

Package_SO

PowerPAK 1212-8 Single (https://www.vishay.com/docs/71656/ppak12128.pdf, https://www.vishay.com/docs/72597/72597.pdf)

Pads: 5
SMD: 4.4×3.6
Boards: 39

SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm_ThermalVias

FP—

Package_SO

SOIC, 8 Pin (http://www.allegromicro.com/~/media/Files/Datasheets/A4950-Datasheet.ashx#page=8)

Pads: 9
SMD: 7.4×5.4
Boards: 38

Texas_HSOP-8-1EP_3.9x4.9mm_P1.27mm_ThermalVias

FP—

Package_SO

Texas Instruments HSOP 9, 1.27mm pitch, 3.9x4.9mm body, exposed pad, thermal vias, DDA0008J (http://www.ti.com/lit/ds/symlink/tps5430.pdf)

Pads: 9
SMD: 7.5×5.5
Boards: 34

HTSSOP-16-1EP_4.4x5mm_P0.65mm_EP3.4x5mm_Mask2.46x2.31mm_ThermalVias

FP—

Package_SO

HTSSOP, 16 Pin (Texas Instruments PWP0016C, based on JEDEC MO-153 variation ABT, 1.00mm body thickness, https://www.ti.com/lit/ml/pptd023ac/pptd023ac.pdf, https://www.ti.com/lit/ds/symlink/drv8833.pdf#page=27, https://www.jedec.org/document_search?search_api_views_fulltext=MO-153)

Pads: 17
SMD: 7.8×5.5
Boards: 31

TSOP-5_1.65x3.05mm_P0.95mm

FP3D

Package_SO

TSOP-5 package (comparable to TSOT-23), https://www.vishay.com/docs/71200/71200.pdf

Pads: 5
SMD: 3.5×3.5
Boards: 30

HSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.1mm_ThermalVias

FP3D

Package_SO

HSOP, 8 Pin (https://www.st.com/resource/en/datasheet/l5973d.pdf)

Pads: 9
SMD: 7.4×5.4
Boards: 28

SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.95x4.9mm_Mask2.71x3.4mm_ThermalVias

FP—

Package_SO

SOIC, 8 Pin (JEDEC MS-012 variation BA (thermally enhanced), using tolerances and Exposed Pad from Texas Instruments DDA0008B, https://www.ti.com/lit/ml/pptd058j/pptd058j.pdf, https://www.ti.com/lit/ds/symlink/lm5017.pdf#page=35, https://www.jedec.org/document_search?search_api_views_fulltext=MS-012)

Pads: 9
SMD: 7.4×5.4
Boards: 16

HTSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.4x3.2mm_ThermalVias

FP3D

Package_SO

HTSOP, 8 Pin (https://media.digikey.com/pdf/Data%20Sheets/Rohm%20PDFs/BD9G341EFJ.pdf)

Pads: 9
SMD: 7.4×5.4
Boards: 14

HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x5.4mm_ThermalVias

FP—

Package_SO

HTSSOP, 28 Pin (https://pdfserv.maximintegrated.com/package_dwgs/21-0108.PDF)

Pads: 29
SMD: 7.7×10.2
Boards: 13

SSO-8_6.8x5.9mm_P1.27mm_Clearance8mm

FP3D

Package_SO

8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true

Pads: 8
SMD: 13.1×6.4
Boards: 13

SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.81mm_ThermalVias

FP3D

Package_SO

SOIC, 8 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ada4898-1_4898-2.pdf#page=29)

Pads: 9
SMD: 7.4×5.4
Boards: 11

HTSSOP-16-1EP_4.4x5mm_P0.65mm_EP3.4x5mm_Mask3x3mm_ThermalVias

FP—

Package_SO

16-Lead Plastic HTSSOP (4.4x5x1.2mm); Thermal pad with vias; (http://www.ti.com/lit/ds/symlink/drv8800.pdf)

Pads: 17
SMD: 7.0×5.7
Boards: 9

HTSSOP-24-1EP_4.4x7.8mm_P0.65mm_EP3.4x7.8mm_Mask2.4x4.68mm_ThermalVias

FP3D

Package_SO

HTSSOP, 24 Pin (http://www.ti.com/lit/ds/symlink/tps703.pdf)

Pads: 25
SMD: 7.8×8.3
Boards: 9

HTSSOP-32-1EP_6.1x11mm_P0.65mm_EP5.2x11mm_Mask4.11x4.36mm_ThermalVias

FP3D

Package_SO

HTSSOP32: plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot487-1_po.pdf)

Pads: 33
SMD: 9.0×11.6
Boards: 9