Footprints
78 footprints matching “thermal”
Land patterns on their own — 19,830 of them, most never referenced by a symbol in the catalog. Each passed the courtyard and pad checks; 7,626 come with the 3D model they name.
TI_SO-PowerPAD-8_ThermalVias
Package_SO
8-pin HTSOP package with 1.27mm pin pitch, compatible with SOIC-8, 3.9x4.9mm² body, exposed pad, thermal vias with large copper area, as proposed in http://www.ti.com/lit/ds/symlink/tps5430.pdf
- Pads
- 9
- SMD
- 7.5×5.5
- Boards
- 103
Texas_HTSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.95x4.9mm_Mask2.4x3.1mm_ThermalVias
Package_SO
8-pin HTSOP package with 1.27mm pin pitch, compatible with SOIC-8, 3.9x4.9mm body, exposed pad, thermal vias, http://www.ti.com/lit/ds/symlink/drv8870.pdf
- Pads
- 9
- SMD
- 8.4×5.5
- Boards
- 47
SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm_ThermalVias
Package_SO
SOIC, 8 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ada4898-1_4898-2.pdf#page=29)
- Pads
- 9
- SMD
- 7.4×5.4
- Boards
- 40
SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm_ThermalVias
Package_SO
SOIC, 8 Pin (http://www.allegromicro.com/~/media/Files/Datasheets/A4950-Datasheet.ashx#page=8)
- Pads
- 9
- SMD
- 7.4×5.4
- Boards
- 38
Texas_HSOP-8-1EP_3.9x4.9mm_P1.27mm_ThermalVias
Package_SO
Texas Instruments HSOP 9, 1.27mm pitch, 3.9x4.9mm body, exposed pad, thermal vias, DDA0008J (http://www.ti.com/lit/ds/symlink/tps5430.pdf)
- Pads
- 9
- SMD
- 7.5×5.5
- Boards
- 34
HTSSOP-16-1EP_4.4x5mm_P0.65mm_EP3.4x5mm_Mask2.46x2.31mm_ThermalVias
Package_SO
HTSSOP, 16 Pin (Texas Instruments PWP0016C, based on JEDEC MO-153 variation ABT, 1.00mm body thickness, https://www.ti.com/lit/ml/pptd023ac/pptd023ac.pdf, https://www.ti.com/lit/ds/symlink/drv8833.pdf#page=27, https://www.jedec.org/document_search?search_api_views_fulltext=MO-153)
- Pads
- 17
- SMD
- 7.8×5.5
- Boards
- 31
HSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.1mm_ThermalVias
Package_SO
HSOP, 8 Pin (https://www.st.com/resource/en/datasheet/l5973d.pdf)
- Pads
- 9
- SMD
- 7.4×5.4
- Boards
- 28
SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.95x4.9mm_Mask2.71x3.4mm_ThermalVias
Package_SO
SOIC, 8 Pin (JEDEC MS-012 variation BA (thermally enhanced), using tolerances and Exposed Pad from Texas Instruments DDA0008B, https://www.ti.com/lit/ml/pptd058j/pptd058j.pdf, https://www.ti.com/lit/ds/symlink/lm5017.pdf#page=35, https://www.jedec.org/document_search?search_api_views_fulltext=MS-012)
- Pads
- 9
- SMD
- 7.4×5.4
- Boards
- 16
HTSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.4x3.2mm_ThermalVias
Package_SO
HTSOP, 8 Pin (https://media.digikey.com/pdf/Data%20Sheets/Rohm%20PDFs/BD9G341EFJ.pdf)
- Pads
- 9
- SMD
- 7.4×5.4
- Boards
- 14
HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x5.4mm_ThermalVias
Package_SO
HTSSOP, 28 Pin (https://pdfserv.maximintegrated.com/package_dwgs/21-0108.PDF)
- Pads
- 29
- SMD
- 7.7×10.2
- Boards
- 13
SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.81mm_ThermalVias
Package_SO
SOIC, 8 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ada4898-1_4898-2.pdf#page=29)
- Pads
- 9
- SMD
- 7.4×5.4
- Boards
- 11
HTSSOP-16-1EP_4.4x5mm_P0.65mm_EP3.4x5mm
Package_SO
16-Lead Plastic HTSSOP (4.4x5x1.2mm); Thermal pad; (http://www.ti.com/lit/ds/symlink/drv8833.pdf)
- Pads
- 17
- SMD
- 7.0×5.7
- Boards
- 10
HTSSOP-16-1EP_4.4x5mm_P0.65mm_EP3.4x5mm_Mask3x3mm_ThermalVias
Package_SO
16-Lead Plastic HTSSOP (4.4x5x1.2mm); Thermal pad with vias; (http://www.ti.com/lit/ds/symlink/drv8800.pdf)
- Pads
- 17
- SMD
- 7.0×5.7
- Boards
- 9
HTSSOP-24-1EP_4.4x7.8mm_P0.65mm_EP3.4x7.8mm_Mask2.4x4.68mm_ThermalVias
Package_SO
HTSSOP, 24 Pin (http://www.ti.com/lit/ds/symlink/tps703.pdf)
- Pads
- 25
- SMD
- 7.8×8.3
- Boards
- 9
HTSSOP-32-1EP_6.1x11mm_P0.65mm_EP5.2x11mm_Mask4.11x4.36mm_ThermalVias
Package_SO
HTSSOP32: plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot487-1_po.pdf)
- Pads
- 33
- SMD
- 9.0×11.6
- Boards
- 9
Texas_R-PDSO-G8_EP2.95x4.9mm_Mask2.4x3.1mm_ThermalVias
Package_SO
HSOIC, 8 Pin (http://www.ti.com/lit/ds/symlink/lmr14030.pdf#page=28, http://www.ti.com/lit/ml/msoi002j/msoi002j.pdf)
- Pads
- 9
- SMD
- 7.4×5.4
- Boards
- 9
HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP3.4x9.5mm_ThermalVias
Package_SO
HTSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; thermal pad
- Pads
- 29
- SMD
- 7.3×10.3
- Boards
- 8
SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.62x3.51mm_ThermalVias
Package_SO
SOIC, 8 Pin (https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/MP2303A/document_id/494#page=14)
- Pads
- 9
- SMD
- 7.4×5.4
- Boards
- 7
HTSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3.4x6.5mm_Mask2.75x3.43mm_ThermalVias
Package_SO
HTSSOP, 20 Pin (http://www.ti.com/lit/ds/symlink/tlc5971.pdf#page=37&zoom=160,-90,3)
- Pads
- 21
- SMD
- 7.8×7.0
- Boards
- 6
MSOP-8-1EP_3x3mm_P0.65mm_EP1.68x1.88mm_ThermalVias
Package_SO
MSOP, 8 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/4440fb.pdf#page=13)
- Pads
- 9
- SMD
- 6.3×3.5
- Boards
- 5
SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.95x4.9mm_Mask2.71x3.4mm
Package_SO
SOIC, 8 Pin (JEDEC MS-012 variation BA (thermally enhanced), using tolerances and Exposed Pad from Texas Instruments DDA0008B, https://www.ti.com/lit/ml/pptd058j/pptd058j.pdf, https://www.ti.com/lit/ds/symlink/lm5017.pdf#page=35, https://www.jedec.org/document_search?search_api_views_fulltext=MS-012)
- Pads
- 9
- SMD
- 7.4×5.4
- Boards
- 4
HTSSOP-16-1EP_4.4x5mm_P0.65mm_EP3.4x5mm_Mask2.66x2.46mm_ThermalVias
Package_SO
HTSSOP, 16 Pin (http://www.ti.com/lit/ds/symlink/tps2660.pdf#page=48)
- Pads
- 17
- SMD
- 7.8×5.5
- Boards
- 3
HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.75x6.2mm_ThermalVias
Package_SO
HTSSOP, 28 Pin (https://www.trinamic.com/fileadmin/assets/Support/AppNotes/AN005x-IC_Package_PCB_Footprint_Guidelines_HTSSOP28_rev1.00.pdf)
- Pads
- 29
- SMD
- 7.8×10.2
- Boards
- 3
HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP3.4x9.5mm_Mask2.4x6.17mm_ThermalVias
Package_SO
HTSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; thermal pad
- Pads
- 29
- SMD
- 7.3×10.3
- Boards
- 3
